Abstract: A Static Random Access Memory (SRAM) cell is a latch circuit formed with two inverters each formed with a PMOS transistor and an NMOS transistor. The latch circuit is coupled to a capacitor through a switch. When the switch is switched on, the stability of data stored in the SRAM cell will be enhanced. When the switch is switched off, data can be written to the SRAM cell quickly.

Abstract: A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the polysilicon layer, performing a first etching process to etch the polysilicon layer and the dielectric layer through the hybrid hard mask to form a gate structure, performing a second etching process to form recesses in the substrate at two sides of the gate structure, and performing a SEG process to form epitaxial silicon layers in each recess.

Abstract: A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the polysilicon layer, performing a first etching process to etch the polysilicon layer and the dielectric layer through the hybrid hard mask to form a gate structure, performing a second etching process to form recesses in the substrate at two sides of the gate structure, and performing a SEG process to form epitaxial silicon layers in each recess.

Abstract: A multiple-thread screw includes: a shank having a tapered end portion and a non-tapered portion, the shank defining an axis and a radial plane radiating from the axis; a first spiral thread formed on the non-tapered portion of the shank and having thread turns, each of which has two diametrically disposed points that cooperatively define a diametrical line inclined at a first thread angle with respect to the radial plane; and two second spiral threads formed on the tapered end portion of the shank and twisted in opposite directions. Each of the second spiral threads has thread turns, each of which has two diametrically disposed points that cooperatively define a diametrical line inclined at a second thread angle with respect to the radial plane. The second thread angle is larger than the first thread angle.

Abstract: A multi-film capping layer having a cobalt layer, a barrier layer, and a stuffing layer is disclosed, wherein the barrier layer isolates the cobalt layer from the stuffing layer. The multi-film capping layer is formed on a gate transistor and applicable to a self-aligned silicide (salicide) process, so that a sheet resistance of the salicide layer on conductive regions of the gate transistor is significantly reduced. The stuffing layer further prevents entry of oxygen or moisture to the salicide layer, thus no cobalt oxide is formed when RTP is performed. Without formation of the cobalt oxide, the salicide process is free from the bridging issue and the filament issue.

Abstract: A method of fabricating a metal plug comprises steps of providing a substrate and forming a dielectric layer on the substrate with an opening to expose part of the substrate. The method further comprises steps of forming a metal layer on the dielectric layer, forming a first barrier layer by chemical vapor deposition (CVD) to provide a better step coverage, and forming a second barrier layer by physical vapor deposition (PVD) to make the barrier layer harder and less water absorptive. A metal layer is then formed on the second barrier layer and is removed by etching back to form the metal plug.

Abstract: A method of forming a barrier layer is described. A dielectric layer is formed on a substrate. The dielectric layer comprises an opening exposing a portion of the substrate. A metallic layer, which is conformal to the opening, is formed on the dielectric layer. A first metallic nitride layer, which is conformal to the opening, is formed on the first metallic layer by chemical vapor deposition. The second metallic nitride layer, which is conformal to the opening, is formed on the first metallic nitride layer.

Abstract: A method of fabricating a gate junction conductive structure is described in which a selective silicon deposition method is used to form a silicon layer of a greater area on the polysilicon gate. A metal silicide process is further conducted on the silicon layer to convert the silicon layer to a metal silicide layer. Since the gate junction surface in forming the metal silicide layer is increased, not only the narrow line effect is prevented, the temperature for the thermal treatment process in forming the metal silicide layer is also lower. As a result, the sheet resistance of the metal silicide layer is lower and the device is more stable.

Abstract: A method of fabricating a semiconductor device is described. A conductive layer is formed on a substrate. A spacer is formed on a sidewall of the conductive layer. A thin metallic layer is formed over the substrate. An ion implantation step is performed. A first seeding layer is formed between the first metallic layer and the conductive layer. A second seeding layer is formed between the first metallic layer and the substrate. A second metallic layer is formed over the substrate. An annealing step is performed to form a self-aligned silicide layer on the conductive layer. The first metallic layer and the second metallic layer that do not react are removed.