Abstract: A device for writing data into a memory and a method thereof. The memory comprises a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. The data is divided into a plurality of segments. The segments are written into first memory cells of the memory cells of the memory arrays in sequence. The segments are written into second memory cells of the memory cells of the memory arrays when the first memory cells of the memory cells of the memory arrays are full, and so forth till the operation of writing the segments into the memory is completed.

Abstract: An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

Abstract: An ultra-low power crystal oscillator architecture that draws less than 2 ?A during steady state operation. An amplifier stage is self biased and has input and output clamp circuits that limit its signal swing. Circuit values are selected such that there is sufficient transient load current for the first amplifier stage to oscillate, while at the same time the input and output clamp circuits maintain a sufficiently low swing of the stage such that the steady state average load current is on the order of less than 1 ?A.