Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.

Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.

Abstract: A method includes forming a circuit region over a substrate. The circuit region includes at least one active region extending along a first direction, and at least one gate region extending across the at least one active region and along a second direction transverse to the first direction. At least one first input/output (TO) pattern and at least one second TO pattern are correspondingly formed in different first and second metal layers to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first TO pattern extends along a third direction oblique to both the first direction and the second direction. The at least one second TO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction.

Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect(LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.

Abstract: A method of forming an integrated circuit includes placing a first and a second standard cell layout design of the integrated circuit on a layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height. Placing the first standard cell layout design includes placing a first set of pin layout patterns on a first layout level over a first set of gridlines, extending in a first direction, and having a first width in a second direction. Placing the second standard cell layout design includes placing a second set of pin layout patterns on the first layout level over a second set of gridlines, extending in the first direction, and having a second width in the second direction.

Abstract: A method of forming an integrated circuit includes generating a first and second standard cell layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height different from the first height. The second standard cell layout design is adjacent to the first standard cell layout design. Generating the first standard cell layout design includes generating a first set of pin layout patterns extending in a first direction, being on a first layout level, and having a first width. Generating the second standard cell layout design includes generating a second set of pin layout patterns extending in the first direction, being on the first layout level, and having a second width different from the first width.

Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect(LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.

Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.

Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.

Abstract: A method of generating a layout design of an integrated circuit. The method includes forming a first region having at least two first-type cell rows extending in a first direction. Each one of the first-type cell rows has a first row height measured along a second direction perpendicular to the first direction. The method also includes forming a second region having at least two second-type cell rows extending in the first direction. Each one of the second-type cell rows has a second row height measured along the second direction. The first region is adjacent to the second region, and the first row height of the first-type cell rows is different from the second row height of the second-type cell rows.

Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.

Abstract: A method of generating a layout design of an integrated circuit. The method includes forming a first region having at least two first-type cell rows extending in a first direction. Each one of the first-type cell rows has a first row height measured along a second direction perpendicular to the first direction. The method also includes forming a second region having at least two second-type cell rows extending in the first direction. Each one of the second-type cell rows has a second row height measured along the second direction. The first region is adjacent to the second region, and the first row height of the first-type cell rows is different from the second row height of the second-type cell rows.

Abstract: A method of forming an integrated circuit includes generating a first and second standard cell layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height different from the first height. The second standard cell layout design is adjacent to the first standard cell layout design. Generating the first standard cell layout design includes generating a first set of pin layout patterns extending in a first direction, being on a first layout level, and having a first width. Generating the second standard cell layout design includes generating a second set of pin layout patterns extending in the first direction, being on the first layout level, and having a second width different from the first width.

Abstract: A method of forming an integrated device includes: providing a first via pillar file specifying a first via pillar; providing a second via pillar file specifying a second via pillar; arranging, by a processor, the first via pillar to electrically connect to a circuit cell in a first circuit; arranging an interconnecting path for electrical connection of the first via pillar to another circuit cell in the first circuit; arranging, by the processor, the second via pillar to replace the first via pillar when the first via pillar induces an electromigration (EM) phenomenon; re-routing the interconnecting path with replacement of the first via pillar to generate a second circuit when the first via pillar induces the EM phenomenon; and generating the integrated device according to the second circuit.

Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.

Abstract: A method of forming an integrated device includes: providing a first via pillar file specifying a first via pillar; providing a second via pillar file specifying a second via pillar; arranging, by a processor, the first via pillar to electrically connect to a circuit cell in a first circuit; arranging an interconnecting path for electrical connection of the first via pillar to another circuit cell; arranging, by the processor, the second via pillar to replace the first via pillar when the first via pillar induces an electromigration (EM) phenomenon; re-routing the interconnecting path with replacement of the first via pillar to generate a second circuit when the first via pillar induces the EM phenomenon; and generating the integrated device according to the second circuit.

Abstract: A method of forming an integrated device includes: pre-storing a plurality of via pillars in a storage tool; arranging a first via pillar selected from the plurality of via pillars to electrically connect to a circuit cell in a first circuit; analyzing electromigration (EM) information of the first circuit to determine if the first via pillar induces an EM phenomenon; arranging a second via pillar selected from the plurality of via pillars to replace the first via pillar of the circuit cell to generate a second circuit when the first via pillar induces the EM phenomenon; and generating the integrated device according to the second circuit.

Abstract: A method of forming an integrated device includes: pre-storing a plurality of via pillars in a storage tool; arranging a first via pillar selected from the plurality of via pillars to electrically connect to a circuit cell in a first circuit; analyzing an electromigration information of the first circuit to determine if the first via pillar induces EM phenomenon; arranging a second via pillar selected from the plurality of via pillars to replace the first via pillar of the circuit cell to generate a second circuit when the first via pillar induces EM phenomenon; and generating the integrated device according to the second circuit.

Abstract: Exemplary embodiments for various via pillar structures include one or more first conductors in a first interconnect layer of a semiconductor stack interconnected with one or more second conductors in a second interconnect layer of the semiconductor stack. The one or more first conductors and/or the one or more second conductors within the first interconnect layer and the second interconnect layer, respectively, can traverse multiple directions. In some situations, this allows multiple interconnections to be utilized to interconnect the one or more first conductors and the one or more second conductors. These multiple interconnections can reduce resistance between the one or more first conductors and the one or more second conductors thereby improving performance of signals flowing between the one or more first conductors and the one or more second conductors.

Abstract: In examples described herein, methods for via pillar placement and an integrated circuit design including a via pillar are described. In some instances, a path within an integrated circuit or proposed integrated circuit design can be identified as having negative slack. In such instances, in particular where the path includes a fanout to input pins of receivers, a via pillar can be inserted at a location prior to fanout of the path. The via pillar can be inserted, for example, proximate to the fanout, but between the fanout and an output pin of a driver that is connected to the path.