Patents by Inventor Ming Te Wei
Ming Te Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150349088Abstract: A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.Type: ApplicationFiled: August 10, 2015Publication date: December 3, 2015Inventors: Ming-Te Wei, Shin-Chuan Huang, Yu-Hsiang Hung, Po-Chao Tsao, Chia-Jui Liang, Ming-Tsung Chen, Chia-Wen Liang
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Publication number: 20150347657Abstract: A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask.Type: ApplicationFiled: August 11, 2015Publication date: December 3, 2015Inventors: Po-Chao Tsao, Shih-Fang Hong, Chia-Wei Huang, Ming-Jui Chen, Shih-Fang Tzou, Ming-Te Wei
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Patent number: 9141744Abstract: A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns.Type: GrantFiled: August 15, 2013Date of Patent: September 22, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Chao Tsao, Shih-Fang Hong, Chia-Wei Huang, Ming-Jui Chen, Shih-Fang Tzou, Ming-Te Wei
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Patent number: 9136348Abstract: A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.Type: GrantFiled: March 12, 2012Date of Patent: September 15, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Te Wei, Shin-Chuan Huang, Yu-Hsiang Hung, Po-Chao Tsao, Chia-Jui Liang, Ming-Tsung Chen, Chia-Wen Liang
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Patent number: 9093473Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.Type: GrantFiled: July 15, 2014Date of Patent: July 28, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Te Wei, Wen-Chen Wu, Lung-En Kuo, Po-Chao Tsao
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Publication number: 20150200192Abstract: The present invention provides a semiconductor structure, including a substrate, having a dielectric layer disposed thereon, a first device region and a second device region defined thereon, at least one first trench disposed in the substrate within the first device region, at least one second trench and at least one third trench disposed in the substrate within the second device region, a work function layer, disposed in the second trench and the third trench, wherein the work function layer partially covers the sidewall of the second trench, and entirely covers the sidewall of the third trench, and a first material layer, disposed in the second trench and the third trench, wherein the first material layer covers the work function layer disposed on partial sidewall of the second trench, and entirely covers the work function layer disposed on the sidewall of the third trench.Type: ApplicationFiled: January 13, 2014Publication date: July 16, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Chao Tsao, Yao-Hung Huang, Chien-Ting Lin, Ming-Te Wei
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Patent number: 9048246Abstract: A die seal ring is provided. The die seal ring includes a substrate and a first layer extruding from the substrate. The first layer has a first fin ring structure and a layout of the first fin ring structure has a stamp-like shape. In addition, a method for forming a die seal ring is provided. A substrate having an active region is provided. A patterned sacrificial layer is formed on the substrate. A spacer is formed on the sidewall of the patterned sacrificial layer. The patterned sacrificial layer is removed. The substrate is patterned by using the spacer as a mask, thereby simultaneously forming at least a fin structure of a Fin-FET and a first layer of the die seal ring.Type: GrantFiled: June 18, 2013Date of Patent: June 2, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Te Wei, Po-Chao Tsao, Ching-Li Yang, Chien-Yang Chen, Hui-Ling Chen, Guan-Kai Huang
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Publication number: 20150129980Abstract: A semiconductor structure comprises a substrate, a plurality of fins, an oxide layer and a gate structure. The fins protrude from the substrate and are separated from each other by the oxide layer. The surface of the oxide layer is uniform and even plane. The gate structure is disposed on the fins. The fin height is distance between the top of the fins and the oxide layer, and at least two of the fins have different fin heights.Type: ApplicationFiled: November 13, 2013Publication date: May 14, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jun-Jie Wang, Po-Chao Tsao, Ming-Te Wei, Shih-Fang Tzou
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Publication number: 20150052491Abstract: A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns.Type: ApplicationFiled: August 15, 2013Publication date: February 19, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Chao Tsao, Shih-Fang Hong, Chia-Wei Huang, Ming-Jui Chen, Shih-Fang Tzou, Ming-Te Wei
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Publication number: 20140367835Abstract: A die seal ring is provided. The die seal ring includes a substrate and a first layer extruding from the substrate. The first layer has a first fin ring structure and a layout of the first fin ring structure has a stamp-like shape. In addition, a method for forming a die seal ring is provided. A substrate having an active region is provided. A patterned sacrificial layer is formed on the substrate. A spacer is formed on the sidewall of the patterned sacrificial layer. The patterned sacrificial layer is removed. The substrate is patterned by using the spacer as a mask, thereby simultaneously forming at least a fin structure of a Fin-FET and a first layer of the die seal ring.Type: ApplicationFiled: June 18, 2013Publication date: December 18, 2014Inventors: Ming-Te Wei, Po-Chao Tsao, Ching-Li Yang, Chien-Yang Chen, Hui-Ling Chen, Guan-Kai Huang
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Publication number: 20140322883Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.Type: ApplicationFiled: July 15, 2014Publication date: October 30, 2014Inventors: Ming-Te Wei, Wen-Chen Wu, Lung-En Kuo, Po-Chao Tsao
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Patent number: 8860181Abstract: A thin film resistor structure includes a substrate, a flat bottom ILD (inter layer dielectric) disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD; a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD, and a thin film resistor disposed between the bottom ILD and the top ILD.Type: GrantFiled: March 7, 2012Date of Patent: October 14, 2014Assignee: United Microelectronics Corp.Inventors: Ming-Te Wei, Po-Chao Tsao, Chen-Hua Tsai, Chien-Yang Chen, Chia-Jui Liang, Ming-Tsung Chen
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Patent number: 8816409Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.Type: GrantFiled: July 15, 2010Date of Patent: August 26, 2014Assignee: United Microelectronics Corp.Inventors: Ming-Te Wei, Wen-Chen Wu, Lung-En Kuo, Po-Chao Tsao
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Patent number: 8575034Abstract: The present invention relates to a fabricating method of a semiconductor element. First, a substrate is provided and a first layout structure having a first width is formed on the substrate. Then, an etching mask is formed to cover the first layout structure, and the etching mask exposes a portion of the first layout structure. After that, the first layout structure is etched with the etching mask to form a second layout structure having a second width. The second width is less than the first width. This fabricating method is capable of finishing the fabrication of gate structures in two different directions. Accordingly, the layout flexibility is improved.Type: GrantFiled: October 28, 2011Date of Patent: November 5, 2013Assignee: United Microelectronics CorporationInventors: Ming-Te Wei, Po-Chao Tsao, Ming-Tsung Chen
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Patent number: 8569127Abstract: A method for fabricating a semiconductor device is described. A substrate having thereon a polysilicon resistor is provided. A dielectric layer is formed over the substrate covering the polysilicon resistor. The dielectric layer is etched to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor. A metal silicide layer is formed on the polysilicon resistor in the contact opening. A metal material is filled in the contact opening. A portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor are removed to expose the metal silicide layer. A metal contact is formed over the metal silicide layer.Type: GrantFiled: March 13, 2012Date of Patent: October 29, 2013Assignee: United Microelectronics Corp.Inventors: Chien-Yang Chen, Chen-Hua Tsai, Shih-Fang Hong, Po-Chao Tsao, Ming-Te Wei
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Patent number: 8546962Abstract: A mark structure for measuring the alignment accuracy between a former layer and a latter layer with electron beam inspection (EBI) is described. The mark structure includes multiple divisions, each of which includes at least one region that includes multiple parts each disposed with a pair of a pattern of the former layer and a pattern of the latter layer. In each region, all of the parts have the same distance in a direction between the pattern of the former layer and the pattern of the latter layer. The distance in the direction is varied over the regions of the divisions of the mark structure.Type: GrantFiled: March 8, 2011Date of Patent: October 1, 2013Assignee: United Microelectronics Corp.Inventors: Jun-Chi Huang, Po-Chao Tsao, Ming-Te Wei
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Publication number: 20130241001Abstract: A method for fabricating a semiconductor device is described. A substrate having thereon a polysilicon resistor is provided. A dielectric layer is formed over the substrate covering the polysilicon resistor. The dielectric layer is etched to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor. A metal silicide layer is formed on the polysilicon resistor in the contact opening. A metal material is filled in the contact opening. A portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor are removed to expose the metal silicide layer. A metal contact is formed over the metal silicide layer.Type: ApplicationFiled: March 13, 2012Publication date: September 19, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Yang Chen, Chen-Hua Tsai, Shih-Fang Hong, Po-Chao Tsao, Ming-Te Wei
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Publication number: 20130234261Abstract: A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.Type: ApplicationFiled: March 12, 2012Publication date: September 12, 2013Inventors: Ming-Te Wei, Shin-Chuan Huang, Yu-Hsiang Hung, Po-Chao Tsao, Chia-Jui Liang, Ming-Tsung Chen, Chia-Wen Liang
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Publication number: 20130234292Abstract: A thin film resistor structure includes a substrate, a flat bottom ILD (inter layer dielectric) disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD; a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD, and a thin film resistor disposed between the bottom ILD and the top ILD.Type: ApplicationFiled: March 7, 2012Publication date: September 12, 2013Inventors: Ming-Te Wei, Po-Chao Tsao, Chen-Hua Tsai, Chien-Yang Chen, Chia-Jui Liang, Ming-Tsung Chen
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Publication number: 20130109163Abstract: The present invention relates to a fabricating method of a semiconductor element. First, a substrate is provided and a first layout structure having a first width is formed on the substrate. Then, an etching mask is formed to cover the first layout structure, and the etching mask exposes a portion of the first layout structure. After that, the first layout structure is etched with the etching mask to form a second layout structure having a second width. The second width is less than the first width. This fabricating method is capable of finishing the fabrication of gate structures in two different directions. Accordingly, the layout flexibility is improved.Type: ApplicationFiled: October 28, 2011Publication date: May 2, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Ming-Te WEI, Po-Chao Tsao, Ming-Tsung Chen