Abstract: A mark structure for measuring the alignment accuracy between a former layer and a latter layer with electron beam inspection (EBI) is described. The mark structure includes multiple divisions, each of which includes at least one region that includes multiple parts each disposed with a pair of a pattern of the former layer and a pattern of the latter layer. In each region, all of the parts have the same distance in a direction between the pattern of the former layer and the pattern of the latter layer. The distance in the direction is varied over the regions of the divisions of the mark structure.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.

Abstract: A structure of a memory cell of a static random memory device and a process for fabricating the same are disclosed. The memory cell includes a substrate having an active region including an N-well and a shallow trench isolation structure; a first gate and a second gate formed over the substrate; a halo region, a LLD, and a source and drain region formed on two sides of the first gate; an interlevel dielectric layer covering the substrate, the first and second gates; and a contact penetrating the interlevel dielectric layer and extending to the source and drain region, no halo region is formed under the contact.

Abstract: A method of manufacturing the semiconductor device having a dual fully-silicided gate includes the following steps. A substrate having a first transistor and a second transistor formed thereon is provided, wherein the first transistor includes a first gate and a first source/drain and the second transistor includes a second gate and a second source/drain. The gate height of the first gate is different from that of the second gate. A first silicidation process is performed to respectively transform the first gate and the second gate into a first silicided gate and a second silicided gate simultaneously, wherein the material of the first silicided gate is different from that of the second silicided gate.

Abstract: A semiconductor device having dual fully-silicided gate is provided, which includes a first transistor, a second transistor, a dielectric layer, and an interlayer insulating layer. The first transistor is disposed on the substrate, which includes a first silicided gate and a first source/drain. The second transistor is disposed on the substrate, which includes a second silicided gate and a second source/drain. The material of the first silicided gate is different from the material of the second silicided gate. The first silicided gate and the second silicided gate are formed in one silicidation process. The dielectric layer completely covers the first transistor and the second transistor. The interlayer insulating layer is disposed on the dielectric layer.

Abstract: A valve device includes a base, and a faucet and a spray gun coupled to the base. A valve member is engaged in the base and has a chamber, and includes two valve seats disposed between the chamber and the faucet and between the chamber and the opening. A valve stem is slidably engaged in the valve member and has two plugs for engaging with the valve seats. A spring may bias one plug to engage with one valve seat and for preventing the water from flowing into the spray gun. The water is allowed to flow into the spray gun when the spray gun is actuated.