Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).

Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.

Abstract: A capacitive sensing device includes a switch circuitry, a counter circuit, a comparator circuit, an amplifier circuit including first and second input terminals and an output terminal, and a feedback capacitor coupled between the output terminal and the first input terminal. The switch circuitry transmits a reference voltage to the second input terminal and couples the first input terminal to the output terminal during a first phase, transmits another reference voltage to the second input terminal during a second phase, and adjusts a voltage of the output terminal during a third phase. The counter circuit starts counting and the comparator circuit generates the control signal according to the output voltage and the second reference voltage during the third phase. The counter circuit stops counting according to the control signal to generate a count value indicating a capacitance value change of a capacitor under-test coupled to the first input terminal.

Abstract: Embodiments of the present disclosure relate to a system, a software application, and methods of digital lithography for semiconductor packaging. The method includes comparing positions of vias and via locations, generating position data based on the comparing the positions of vias and the via locations, providing the position data of the vias to a digital lithography device, updating a redistributed metal layer (RDL) mask pattern according to the position data such that RDL locations correspond to the positions of the vias, and projecting the RDL mask pattern with the digital lithography device.

Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) having a portion within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: A method performed by a wireless communication device includes determining whether to transmit a first Sidelink Synchronization Signal (SLSS) according to a priority parameter when an occasion of the first SLSS collides with a Physical Sidelink Feedback Channel (PSFCH) that carries Sidelink Feedback Control Information (SFCI). The priority parameter is associated with a Physical Sidelink Shared Channel (PSSCH) that corresponds to the PSFCH.

Abstract: Some of the present implementations provide a method for a user equipment (UE) for receiving a power saving signal. The method receives, from a base station, a power saving signal comprising a minimum applicable K0 (K0min) that indicates a minimum scheduling offset restriction between a physical downlink control channel (PDCCH) and a physical downlink shared channel (PDSCH). The method determines an application delay based on a predefined value. The method then applies the minimum scheduling offset restriction after the application delay.

Abstract: The present invention discloses a wearable device with combined sensing capabilities, which includes a wearable assembly and at least one multi-function sensor module. The wearable assembly is suitable to be worn on apart of a user's body. The wearable assembly includes at least one light-transmissible window. The multi-function sensor module is located inside the wearable assembly, for performing an image sensing function and an infrared temperature sensing function. The multi-function sensor module includes an image sensor module for sensing a physical or a biological feature of an object through the light-transmissible window by way of image sensing; and an infrared temperature sensor module for sensing temperature through the light-transmissible window by way of infrared temperature sensing.

Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.

Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.

Abstract: A method of forming a semiconductor-on-insulator (SOI) substrate includes: forming a first dielectric layer on a first substrate; forming a buffer layer on a second substrate; forming a semiconductor cap on the buffer layer over the second substrate; forming a cleavage plane in the buffer layer; forming a second dielectric layer on the semiconductor cap after forming the cleavage plane; bonding the second dielectric layer on the second substrate to the first dielectric layer on the first substrate; performing a splitting process along the cleavage plane in the buffer layer; removing a first split buffer layer from the semiconductor cap; and removing a second split buffer layer from the second substrate.

Abstract: A manufacturing method of a flip chip package structure is provided and has following steps: providing at least one silicon substrate having a connecting surface and at least one conductive base attached to the connecting surface; arranging a graphene copper layer covering the conductive base; laminating a photoresist layer on the connecting surface, etching the photoresist layer to form a cavity corresponding to the conductive base, and a portion of the graphene copper layer corresponding to the conductive base being exposed on a bottom of the cavity; electroplating a copper material on the graphene copper layer, and the copper material being accumulated in the cavity to form a copper pillar; removing the photoresist layer and the graphene copper layer covered by the photoresist layer.

Abstract: An atomization device and a method of predicting atomization time for the same are provided. The atomization device includes a control module, an atomization module and a breathing sensing module. The method includes: configuring the breath sensing module to detect inhalations of a user using the atomization device, so as to generate initial breath data correspondingly; and configuring the control module to perform: comparing inhalation data of the initial breath data with a valid inhalation standard to obtain valid inhalation data and filter noise; statistically analyzing the valid inhalation data to generate a predicted value of inhalation time; calculating an atomization time according to the predicted value of the inhalation time; and generating a driving signal to drive the atomization module to perform atomization according to the atomization time.

Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.

Abstract: A light-emitting device includes a semiconductor epitaxial structure including a first semiconductor layer, an active layer, and a second semiconductor layer, and having holes; a first insulation layer disposed on the semiconductor epitaxial structure and having first and second grooves; a first pad electrically connected to the first semiconductor layer through the first grooves; and a second pad electrically connected to the second semiconductor layer through the second grooves. A projection of the first pad does not overlap projections of the holes. A projection of the second pad does not overlap the projections of the holes. The first pad includes a first pad connection portion and first pad extension portions; the second pad includes a second pad connection portion and second pad extension portions. Projections of the second grooves fall between projections of the first and second pad extension portions. Two other aspects of the light-emitting device are also provided.

Abstract: A semiconductor light emitting device includes a multi-quantum-well structure, a first capping layer, a second capping layer, and an electron barrier layer stacked in order. The multi-quantum-well structure includes a plurality of alternately-stacked potential barrier layers and potential well layers. The first capping layer is a semiconductor layer, and the second capping layer is a p-doped semiconductor layer. Each of the first and second capping layers has an aluminum mole fraction larger than that of each of the potential barrier layers, and the aluminum mole fraction of the first capping layer is larger than that of at least a portion of the electron barrier layer. A method for preparing the semiconductor light emitting device is also provided.

Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a plurality of fin structures above a substrate, an isolation structure over the substrate and between the fin structures, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The FinFET device structure also includes a metal silicide layer over the S/D structure, and the metal silicide layer is in contact with the isolation structure.

Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.