Abstract: A light-emitting device includes a semiconductor epitaxial structure including a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked in such order in a stacking direction, and including a plurality of through holes. The through holes extend downwardly in a direction from the second semiconductor layer to the first semiconductor layer. The through holes expose a portion of a surface of the first semiconductor layer. The light-emitting device has an ampacity. Each of the through holes has a first radius. A ratio of the first radius to the ampacity ranges from 0.1 to 0.4. A light-emitting apparatus including the light-emitting device is also provided.

Abstract: A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.

Abstract: A package structure is provided. The package structure includes a substrate, an electrode layer, a lighting unit, a wall, and a package compound. The substrate and the wall that is disposed on the substrate jointly define an accommodating space. The lighting unit in the accommodating space and is electrically connected to the electrode layer disposed on the substrate. The package compound covers the electrode layer, and the lighting unit. The package compound includes an attaching portion disposed on a top surface of the lighting unit and a surrounding portion that is arranged around the attaching portion. The surrounding portion has an annular slot arranged on a top surface thereof. A bottom end of the annular slot is located at a position aligning with 25%˜90% of a thickness of the lighting diode along a height direction.

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

Abstract: A semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; an electronic component disposed on the first surface of the substrate; a sensor disposed adjacent to the second surface of the substrate; an electrical contact disposed on the first surface of the substrate; and a package body exposing a portion of the electrical contact.

Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A bottom electrode via couples the bottom electrode to a lower interconnect. A top electrode via couples the top electrode to an upper interconnect. A bottommost surface of the top electrode via is directly over the top electrode and has a first width that is smaller than a second width of a bottommost surface of the bottom electrode via.

Abstract: Provided are a package structure and a method of forming the same. The package structure includes a bottom package having a first sidewall and a second sidewall opposite to each other; a hybrid path layer disposed on the bottom package, wherein the hybrid path layer comprises an optical path layer and an electrical path layer, and at least one optical path of the optical path layer extends from the first sidewall of the bottom package beyond a center of the bottom package; and a plurality of dies bonded onto the hybrid path layer.

Abstract: A lens assembly and Augmented Reality (AR) glasses, including a waveguide substrate, a wiring layer, a protective layer, an eye tracking component, and a lens. The waveguide substrate includes a first surface. The wiring layer is disposed on the first surface. The protective layer is disposed on the first surface and covering the wiring layer. The eye tracking component is disposed in the protective layer and is electrically connected with the wiring layer for tracking position of an eyeball. The lens is connected to a side of the protective layer away from the waveguide substrate. The AR glasses includes a display device and two lens assemblies. The display device is positioned between the two lens assemblies for emitting image light to the waveguide substrates of the two lens assemblies.

Abstract: A circuit, for a touch panel, comprising N touch signal processing circuits; a backup processing circuit; and a controller, coupled to the N touch signal processing circuits and the backup processing circuit, configured to determine whether one of the N touch signal processing circuits is failed and generate a determining result, and control the N touch signal processing circuits and the backup processing circuit to process N touch signals received from the touch panel to obtain N digital signals according to the determining result.

Abstract: A touch event processing circuit includes receiving circuits and an average circuit. Each of the receiving circuits includes an operation amplifier, a current processing circuit, and a touch event detection circuit. The operation amplifier receives an input signal from a touch panel, and outputs a first current signal and a second current signal. The current processing circuit processes the first current signal and the second current signal according to a first current average signal and a second current average signal, to generate a processed current signal. The touch event detection circuit detects a touch event according to the processed current signal. The average circuit receives first current signals and second current signals from the receiving circuits; performs an average operation upon the first current signals, to generate the first current average signal; and performs an average operation upon the second current signals, to generate the second current average signal.

Abstract: A manufacturing method of a flip chip package structure is provided and has following steps: providing at least one silicon substrate having a connecting surface and at least one conductive base attached to the connecting surface; arranging a graphene copper layer covering the conductive base; laminating a photoresist layer on the connecting surface, etching the photoresist layer to form a cavity corresponding to the conductive base, and a portion of the graphene copper layer corresponding to the conductive base being exposed on a bottom of the cavity; electroplating a copper material on the graphene copper layer, and the copper material being accumulated in the cavity to form a copper pillar; removing the photoresist layer and the graphene copper layer covered by the photoresist layer.

Abstract: A display light engine which includes a light source module, a spectrum conversion array disposed on the light source module and a lens array is provided. The light source module includes a plurality of light-emitting components which emit light toward the spectrum conversion array. The spectrum conversion array includes a plurality of spectrum conversion components and a metal bank material. The spectrum conversion components are spaced from each other and are disposed on the light-emitting components respectively. The metal bank material is distributed between two adjacent spectrum conversion components and separates the spectrum conversion components from each other. The lens array which includes a plurality of lenses arranged in an array is disposed between the spectrum conversion array and the light source module. Those lenses are disposed on and align to the spectrum conversion components respectively.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: A method for a base station (BS) instructing a UE to monitor a physical downlink control channel (PDCCH) for power saving signaling is disclosed. The method comprises transmitting a discontinuous reception (DRX) configuration to the UE indicating to monitor a scheduling signal on the PDCCH within a DRX active time, and transmitting a configuration to the UE for monitoring the power saving signaling on the PDCCH, instructing the UE to wake up for monitoring the scheduling signal in the DRX active time, wherein the configuration includes a time in milliseconds prior to a start of a DRX on-duration time, and instructs the UE to start monitoring the PDCCH for the power saving signaling.

Abstract: A semiconductor package includes an encapsulated semiconductor device, a backside redistribution structure, and a front side redistribution structure. The encapsulated semiconductor device includes an encapsulating material and a semiconductor device encapsulated by the encapsulating material. The backside redistribution structure is disposed on a backside of the encapsulated semiconductor device and includes a redistribution circuit layer and a first patterned dielectric layer. The redistribution circuit layer has a circuit pattern and a dummy pattern electrically insulated from the circuit pattern. The dummy pattern is overlapped with the semiconductor device from a top view of the semiconductor package. The first patterned dielectric layer is disposed on the redistribution circuit layer and includes a marking pattern disposed on the dummy pattern and revealing a part of the dummy pattern.

Abstract: There is provided a smoke detector including a substrate, a light source and a light sensor. The light source and the light sensor are arranged adjacently on the substrate. The substrate is arranged with an asymmetric structure to cause an illumination region of the light source to deviate toward the light sensor thereby increasing a ratio of light intensity reflected by smoke with respect to reference light intensity.

Abstract: a combination socket comprises a socket surface that can accommodate multiple different specifications of IEC plugs. This socket surface has recessed grooves, socket cores, and socket holes; the surface of the socket core is equipped with live wire socket holes, neutral wire socket holes, and ground wire socket holes; the grooves include a wide groove located in front of the socket core and a narrow groove located behind the socket core.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.