Patents by Inventor Ming Tsai
Ming Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250260828Abstract: A method for performing template-based intra mode derivation (TIMD) with enhanced candidate intra-prediction modes is provided. A video coder determines a set of most probable modes (MPMs) for intra-coding the current block based on intra-prediction modes used to code neighboring blocks of the current block. The video coder determines a template of the current block among already-reconstructed pixels neighboring the current block. The video coder determines a set of candidate intra-prediction modes to include (i) the set of MPMs and (ii) one or more intra-prediction modes neighboring an MPM in the set of MPMs. The video coder derives an intra-prediction mode from the set of candidate intra-prediction modes based on the determined template and the set of candidate intra-prediction modes. The video coder encodes or decodes the current block by using the derived intra-prediction mode to generate an intra-prediction.Type: ApplicationFiled: April 14, 2023Publication date: August 14, 2025Inventors: Chia-Ming TSAI, Chun-Chia CHEN, Man-Shu CHIANG, Yu-Cheng LIN, Tzu-Der CHUANG, Chih-Wei HSU, Ching-Yeh CHEN, Yu-Wen HUANG
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Patent number: 12386264Abstract: Embodiments described herein relate to methods of printing double exposure patterns in a lithography environment. The methods include determining a second exposure pattern to be exposed with a first exposure pattern in a lithography process. The second exposure pattern is determined with a rule-based process flow or a lithography model process flow.Type: GrantFiled: September 9, 2021Date of Patent: August 12, 2025Assignee: Applied Materials, Inc.Inventor: Chi-Ming Tsai
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Publication number: 20250255038Abstract: A semiconductor light emitting device includes a multi-quantum-well structure, a first capping layer, a second capping layer, and an electron barrier layer stacked in order. The multi-quantum-well structure includes a plurality of alternately-stacked potential barrier layers and potential well layers. The first capping layer is a semiconductor layer, and the second capping layer is a p-doped semiconductor layer. Each of the first and second capping layers has an aluminum mole fraction larger than that of each of the potential barrier layers, and the aluminum mole fraction of the first capping layer is larger than that of at least a portion of the electron barrier layer. A method for preparing the semiconductor light emitting device is also provided.Type: ApplicationFiled: April 25, 2025Publication date: August 7, 2025Inventors: Yung-Ling LAN, Chan-Chan LING, Chi-Ming TSAI, Chia-Hung CHANG
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Publication number: 20250254292Abstract: Methods and apparatus for video coding are disclosed. According to one method, a selected set of angular intra prediction candidate modes corresponding to a subset of an initial set of angular intra prediction modes is used to derive DIMD candidates. In another method, a delta angle between the final intra prediction mode and a DIMD derived mode is signalled or parsed. In yet another method, a DIMD candidate mode is determined by using a process including comparing gradient magnitudes of the gradient filtered results with a threshold.Type: ApplicationFiled: April 12, 2023Publication date: August 7, 2025Inventors: Chia-Ming TSAI, Chun-Chia CHEN, Man-Shu CHIANG, Yu-Cheng LIN, Tzu-Der CHUANG, Chih-Wei HSU, Ching-Yeh CHEN, Yu-Wen HUANG
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Publication number: 20250254300Abstract: Methods and apparatus for video coding. A current block is partitioned into one or more sub-blocks. The partitioning process comprises: signalling or parsing a first syntax where the first syntax is indicative of whether to split the current block; and in response to the first syntax indicating the current block being split, signalling or parsing a second syntax where the second syntax is indicative of whether to use a shortcut mode to indicate a target partition from predefined partitions directly. The sub-blocks are then encoded or decoded. According to another method, the partitioning process comprises signalling or parsing a first syntax where the first syntax is indicative of whether to split the current block; and in response to the first syntax, signalling or parsing a second syntax where the second syntax is indicative of one or more conditions comprising whether one of predefined partitions being applied to the current block.Type: ApplicationFiled: April 11, 2023Publication date: August 7, 2025Inventors: Chih-Yao CHIU, Hong-Hui CHEN, Chun-Chia CHEN, Shih-Ta HSIANG, Chia-Ming TSAI, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
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Publication number: 20250255046Abstract: A light emitting diode is provided. The light emitting diode includes: a semiconductor stack, including a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a first insulating layer, formed on the semiconductor stack; a reflective electrode layer, partially formed on the first insulating layer, wherein a minimum distance between an edge of the reflective electrode layer and the semiconductor stack is a fourth distance, and the fourth distance is in a range of 1 ?m to 5 ?m; and a fourth insulating layer, formed on the reflective electrode layer, wherein the fourth insulating layer is aluminum oxide.Type: ApplicationFiled: April 22, 2025Publication date: August 7, 2025Applicant: Xiamen San'an Optoelectronics Co., Ltd.Inventors: Xiushan ZHU, Yan LI, Ji CHEN, Qi JING, Zhilong LU, Chi-ming TSAI, Juchin TU, Chung-ying CHANG
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Publication number: 20250241055Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.Type: ApplicationFiled: April 11, 2025Publication date: July 24, 2025Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming TSAI, Ming-Te CHEN, Shih-Chi LIN, Zack CHONG, Tien-Wei YU
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Publication number: 20250234034Abstract: A method and apparatus for video coding. According to the method for the decoder side, coded data associated with a current block to be decoded is received. A curved intra prediction model associated with a curved intra prediction mode is determined for the current block, where the curved intra prediction model is derived based on a template of the current block or based on decoder side intra mode derivation using statistics or histogram of angle field derived from the template of the current block. The template comprises at least 3 lines in a neighbouring region of the current block. The current block is decoded using one or more intra prediction mode candidates including the curved intra prediction mode.Type: ApplicationFiled: February 8, 2023Publication date: July 17, 2025Inventors: Chia-Ming TSAI, Chun-Chia CHEN, Man-Shu CHIANG, Yu-Cheng LIN, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
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Patent number: 12360220Abstract: A LiDAR and a method of a fast photon-count integration for a LiDAR are disclosed. The proposed method, wherein the LiDAR includes a laser, includes: providing a target and the LiDAR; causing the laser to fire a laser pulse towards the target according to a random mechanism; and causing an interval between two adjacent laser pulses to be less than a time that the laser spent for a round trip of maximum unambiguous range to speed up a detection and a ranging of the target.Type: GrantFiled: November 18, 2021Date of Patent: July 15, 2025Assignee: National Yang Ming Chiao Tung UniversityInventors: Tzu-Hsien Sang, Chia-Ming Tsai, Yung-Chien Liu, Ningkai Yang, Ting-Yuan Wang
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Publication number: 20250212560Abstract: Disclosed are a semiconductor epitaxial structure, a preparation method thereof, and a light-emitting diode. The semiconductor epitaxial structure includes a buffer layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer that are sequentially arranged on a substrate. The material of the buffer layer is AlxInyGa(1-x-y)N, wherein 0x and 0?y. The buffer layer is doped with carbon impurities. The doping concentration of the carbon impurities in the buffer layer is lower than 9E17 atoms/cm3. The present invention grows the buffer layer using a high-temperature growth method. The buffer layer has a lower defect density and a lower content of carbon impurities, making it more possible to facilitate enhancement of the lattice quality of the subsequent epitaxial structure and improve the luminous efficiency and anti-aging capability of the light-emitting diode.Type: ApplicationFiled: December 3, 2024Publication date: June 26, 2025Applicant: Xiamen San'an Optoelectronics Co., Ltd.Inventors: Menghsin YEH, Zhousheng JIANG, Chi-ming TSAI, Chungying CHANG
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Patent number: 12340163Abstract: A method for forming a photomask includes following operations. A first photomask is received. The first photomask includes a first pattern and a first scattering bar. The first photomask is used to remove a first portion of a target layer to form a first opening and a second opening. The first opening corresponds to the first pattern, and the second opening corresponds to the first scattering bar. A second photomask is received. The second photomask includes a second pattern. The second photomask is used to remove a second portion of the target layer to form a third opening. The third opening corresponds to the second pattern. The second opening is widened to form the third opening using the second photomask.Type: GrantFiled: April 25, 2023Date of Patent: June 24, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Min Huang, Ching-Hung Lai, Jia-Guei Jou, Yin-Chuan Chen, Chi-Ming Tsai
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Patent number: 12336265Abstract: The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.Type: GrantFiled: January 9, 2023Date of Patent: June 17, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Wei Wang, Chia-Ming Tsai, Ke-Chih Liu, Chandrashekhar Prakash Savant, Tien-Wei Yu
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Publication number: 20250193394Abstract: A method for signaling arbitrary partition boundaries is provided. A video coder derives a partitioning structure for splitting the current block by identifying a partitioning position having a lowest cost. The video coder splits the current block into first and second partitions according to the identified partitioning position. The video coder encodes or decodes the first and second partitions of the current block. The first and second partitions may be associated with first and second templates that are constructed based on reconstructed pixels neighboring the current block. The video coder may identify the partitioning position by computing a first cost based on the first template and a second cost based on the second template and optimizing the partitioning position to minimize a sum of the first and second costs.Type: ApplicationFiled: April 10, 2023Publication date: June 12, 2025Inventors: Hong-Hui CHEN, Chun-Chia CHEN, Shih-Ta HSIANG, Chia-Ming TSAI, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
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Patent number: 12328973Abstract: Disclosed is a multi-quantum well structure including a stress relief layer, an electron-collecting layer disposed on the stress relief layer, and an active layer including a first active layer unit that is disposed on the electron-collecting layer. The first active layer unit includes potential barrier sub-layers and potential well sub-layers being alternately stacked, in which at least one of the potential barrier sub-layers has a GaN/Alx1Iny1Ga(1-x1-y1)N stack, where 0<x1?1 and 0?y1<1. An LED device including the multi-quantum well structure is also disclosed.Type: GrantFiled: November 17, 2021Date of Patent: June 10, 2025Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.Inventors: Han Jiang, Yung-Ling Lan, Wen-Pin Huang, Changwei Song, Li-Cheng Huang, Feilin Xun, Chan-Chan Ling, Chi-Ming Tsai, Chia-Hung Chang
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Publication number: 20250176317Abstract: A light-emitting diode (LED) includes a semiconductor laminated layer including a first semiconductor layer, a light-emitting layer, and a second semiconductor layer arranged sequentially; a transparent conductive layer disposed on an upper surface of the second semiconductor layer; and an insulating structure, covering the semiconductor laminated layer and the transparent conductive layer. The insulating structure defines a first opening and a second opening, the first opening is located on the first semiconductor layer, and the second opening is located on the transparent conductive layer. The transparent conductive layer defines a groove corresponding to the second opening. With this arrangement, the electrostatic discharge resistance and light-emitting performance of the LED can be effectively enhanced and the quality of the LED can be improved.Type: ApplicationFiled: November 20, 2024Publication date: May 29, 2025Inventors: JIANGBIN ZENG, GUANGYAO WU, KAI ZHAO, CHAO LU, QING WANG, LING-YUAN HONG, SHAO-HUA HUANG, CHI-MING TSAI, CHUNG-YING CHANG
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Publication number: 20250176318Abstract: A light emitting diode includes a semiconductor stacked layer, including a first semiconductor layer, a light-emitting layer and a second semiconductor layer sequentially stacked in that order, and having a mesa being an upper surface of the first semiconductor layer that is not covered by the light-emitting layer; and an insulation structure, covering the semiconductor stacked layer, and having a first opening located on the mesa and a second opening located on the second semiconductor layer. The semiconductor stacked layer defines a dimple at the mesa. The first semiconductor layer has a first sloped sidewall at the dimple, the insulation structure has a second sloped sidewall at the mesa, an angle between the first sloped sidewall and a horizontal plane is first angle, an angle between the second sloped sidewall and the horizontal plane is second angle, and the first angle is smaller than or equal to the second angle.Type: ApplicationFiled: November 20, 2024Publication date: May 29, 2025Inventors: Xiushan ZHU, Yan LI, Qi JING, Zhihao BAO, Qingchao YANG, Chunhsien LEE, Chi-Ming TSAI, Juchin TU, Chung-Ying CHANG
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Patent number: 12315730Abstract: A method includes providing a structure having a substrate, a semiconductor channel layer over the substrate, an interfacial oxide layer over the semiconductor channel layer, and a high-k gate dielectric layer over the interfacial oxide layer, wherein the semiconductor channel layer includes germanium. The method further includes forming a metal nitride layer over the high-k gate dielectric layer and performing a first treatment to the structure using a metal-containing gas. After the performing of the first treatment, the method further includes depositing a silicon layer over the metal nitride layer; and then annealing the structure such that a metal intermixing layer is formed over the high-k gate dielectric layer. The metal intermixing layer includes a metal oxide having metal species from the high-k gate dielectric layer and additional metal species from the metal-containing gas.Type: GrantFiled: May 10, 2022Date of Patent: May 27, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chandrashekhar Prakash Savant, Kin Shun Chong, Tien-Wei Yu, Chia-Ming Tsai
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Publication number: 20250159965Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.Type: ApplicationFiled: January 14, 2025Publication date: May 15, 2025Inventors: Wei-Yip Loh, Yan-Ming Tsai, Hung-Hsu Chen, Chih-Wei Chang, Sheng-Hsuan Lin
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Publication number: 20250155797Abstract: Embodiments described herein provide for a system, a software application, and a method of a lithography process to form a three-dimensional profile in a single exposure operation. An image projections system of a lithography system will provide a plurality of shots to a photoresist layer. To form a three-dimensional profile in the photoresist layer, a local shot density of a plurality of shots within an exposure area will be varied. The local shot density will determine a dose provided by the image projection system at each sub-grid of an exposure area. The dose will determine the thickness of a photoresist layer when the plurality of shots are projected to the photoresist layer.Type: ApplicationFiled: December 16, 2021Publication date: May 15, 2025Inventors: Chi-Ming TSAI, Thomas L. LAIDIG
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Patent number: 12302666Abstract: A semiconductor light emitting device includes a multi-quantum-well structure, a first capping layer, a second capping layer, and an electron barrier layer stacked in order. The multi-quantum-well structure includes a plurality of alternately-stacked potential barrier layers and potential well layers. The first capping layer is a semiconductor layer, and the second capping layer is a p-doped semiconductor layer. Each of the first and second capping layers has an aluminum mole fraction larger than that of each of the potential barrier layers, and the aluminum mole fraction of the first capping layer is larger than that of at least a portion of the electron barrier layer. A method for preparing the semiconductor light emitting device is also provided.Type: GrantFiled: December 15, 2023Date of Patent: May 13, 2025Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.Inventors: Yung-Ling Lan, Chan-Chan Ling, Chi-Ming Tsai, Chia-Hung Chang