Patents by Inventor Ming Tsai

Ming Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11870991
    Abstract: Video processing methods include receiving input data of a current block in a current slice, determine determining whether one or more components of the current block satisfy one or more predefined criteria during partitioning, and applying a mode constraint to the current block only if the one or more components of the current block satisfy the one or more predefined criteria, wherein the mode constraint restricts all blocks within the current block to be processed by a same prediction mode when the current block is split into a plurality of blocks. The methods adaptively split the current block into one or more blocks, and pare one or more prediction mode syntax elements of a first block in the current block according to a constrained mode of the current block. The methods further encode the current block with the mode constraint.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: January 9, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Zhi-Yi Lin, Tzu-Der Chuang, Ching-Yeh Chen, Chia-Ming Tsai
  • Patent number: 11865674
    Abstract: A positioning fixture including a shielding member and a driving member is provided. The shielding member includes a sliding part slidably connected to a functional module, a guiding part, and a shielding part. The sliding part and the shielding part respectively extend from two opposite ends of the guiding part. The driving member is movably disposed on the functional module corresponding to the shielding member. The driving member includes a base part, a driving part that contacts the guiding part, and a pillar part, which protrudes from the base part and is adapted to pass through the guiding groove. When the functional module is positioned on the circuit board, the base part of the driving member is pushed by the electronic component, and the guiding part is pushed by the driving part, so that the shielding member slides and the shielding part shields a screw hole of the circuit board.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: January 9, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Chun-Nan Chen, Ming-Te Lin, Chi-Ming Tsai
  • Patent number: 11852216
    Abstract: A transmission system of a decelerating mechanism includes a planetary gear unit including a sun gear being adjacent to the first surface and a planetary gear set and a holder including a carrier and several planetary shaft units rotatably disposed on the carrier. The carrier has a first surface and a second surface that face opposite directions. The planetary gear set has several first gears being adjacent to the first surface, respectively fitting around the planetary shaft units, and meshing with the sun gear, several second gears being adjacent to the second surface and being coaxially disposed with the first gears, and an internal gear ring meshing with the second gears. By respectively arranging the first gears and the second gears on two opposite sides of the carrier, mutual interference therebetween while turning could be avoided, and an overall volume of the transmission system could be reduced.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: December 26, 2023
    Assignee: TIEN HSIN INDUSTRIES CO., LTD.
    Inventors: Ming-Lan Ou, Tsung-Ming Tsai, Yu-Nong Wu
  • Patent number: 11855189
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate structure, and source/drain structures. The semiconductor fin extends upwardly from the substrate. The gate structure is across the semiconductor fin and includes a high-k dielectric layer over the semiconductor fin, a fluorine-containing work function layer over the high-k dielectric layer and comprising fluorine, a tungsten-containing layer over the fluorine-containing work function layer, and a metal gate electrode over the tungsten-containing layer. The source/drain structures are on the semiconductor fin and at opposite sides of the gate structure.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar P. Savant, Tien-Wei Yu, Ke-Chih Liu, Chia-Ming Tsai
  • Publication number: 20230411496
    Abstract: A semiconductor structure and method of forming a semiconductor structure are provided. In some embodiments, the method includes forming a gate structure over a substrate. An epitaxial source/drain region is formed adjacent to the gate structure. A dielectric layer is formed over the epitaxial source/drain region. An opening is formed, the opening extending through the dielectric layer and exposing the epitaxial source/drain region. Sidewalls of the opening are defined by the dielectric layer and a bottom of the opening is defined by the epitaxial source/drain region. A silicide layer is formed on the epitaxial source/drain region. A metal capping layer including tungsten, molybdenum, or a combination thereof is selectively formed on the silicide layer by a first deposition process. The opening is filled with a first conductive material in a bottom-up manner from the metal capping layer by a second deposition process different from the first deposition process.
    Type: Application
    Filed: May 23, 2022
    Publication date: December 21, 2023
    Inventors: Kan-Ju LIN, Chien CHANG, Chih-Shiun CHOU, Tai Min CHANG, Yi-Ning TAI, Hong-Mao LEE, Yan-Ming TSAI, Wei-Yip LOH, Harry CHIEN, Chih-Wei CHANG, Ming-Hsing TSAI, Lin-Yu HUANG
  • Patent number: 11848401
    Abstract: A semiconductor light emitting device includes a multi-quantum-well structure, a first capping layer, a second capping layer, and an electron barrier layer stacked in order. The multi-quantum-well structure includes a plurality of alternately-stacked potential barrier layers and potential well layers. The first capping layer is a semiconductor layer, and the second capping layer is a p-doped semiconductor layer. Each of the first and second capping layers has an aluminum mole fraction larger than that of each of the potential barrier layers, and the aluminum mole fraction of the first capping layer is larger than that of at least a portion of the electron barrier layer. A method for preparing the semiconductor light emitting device is also provided.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: December 19, 2023
    Assignee: Xiamen San'An Optoelectronics Co., Ltd.
    Inventors: Yung-Ling Lan, Chan-Chan Ling, Chi-Ming Tsai, Chia-Hung Chang
  • Publication number: 20230402278
    Abstract: A method of forming a semiconductor device includes following operations. A substrate is provided with a gate stack thereon, an epitaxial layer therein, and a dielectric layer aside the gate stack and over the epitaxial layer. An opening is formed through the dielectric layer, and the opening exposes the epitaxial layer. A metal silicon-germanide layer is formed on the epitaxial layer, wherein the metal silicon-germanide layer includes a metal having a melting point of about 1700° C. or higher. A connector is formed over the metal silicon-germanide layer in the opening.
    Type: Application
    Filed: June 12, 2022
    Publication date: December 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yan-Ming Tsai, Wei-Yip Loh, Harry CHIEN, Chih-Shiun Chou, Hong-Mao Lee, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20230393693
    Abstract: A capacitive sensing device includes a switch circuitry, a counter circuit, a comparator circuit, an amplifier circuit including first and second input terminals and an output terminal, and a feedback capacitor coupled between the output terminal and the first input terminal. The switch circuitry transmits a reference voltage to the second input terminal and couples the first input terminal to the output terminal during a first phase, transmits another reference voltage to the second input terminal during a second phase, and adjusts a voltage of the output terminal during a third phase. The counter circuit starts counting and the comparator circuit generates the control signal according to the output voltage and the second reference voltage during the third phase. The counter circuit stops counting according to the control signal to generate a count value indicating a capacitance value change of a capacitor under-test coupled to the first input terminal.
    Type: Application
    Filed: May 16, 2023
    Publication date: December 7, 2023
    Inventor: HSU-MING TSAI
  • Publication number: 20230387316
    Abstract: A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuen-Shin LIANG, Min-Chiang CHUANG, Chia-Cheng CHEN, Chun-Hung WU, Liang-Yin CHEN, Sung-Li WANG, Pinyen LIN, Kuan-Kan HU, Jhih-Rong HUANG, Szu-Hsian LEE, Tsun-Jen CHAN, Cheng-Wei LIAN, Po-Chin CHANG, Chuan-Hui SHEN, Lin-Yu HUANG, Yuting CHENG, Yan-Ming TSAI, Hong-Mao LEE
  • Publication number: 20230377994
    Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 23, 2023
    Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming Tsai, Ming-Te Chen, Tien-Wei Yu
  • Publication number: 20230369130
    Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Wei-Yip Loh, Yan-Ming Tsai, Hung-Hsu Chen, Chih-Wei Chang, Sheng-Hsuan Lin
  • Publication number: 20230367943
    Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Chi-Ta Lu, Chi-Ming Tsai
  • Patent number: 11817528
    Abstract: A nitride-based light-emitting diode (LED) device includes an n-type nitride semiconductor layer, an active layer disposed on the n-type nitride semiconductor layer, a p-type nitride semiconductor layer disposed on the active layer, and a defect control unit disposed between the n-type nitride semiconductor layer and the active layer. The defect control unit includes first, second and third defect control layers that are sequentially disposed on the n-type nitride semiconductor layer, and that have different doping concentrations. The third defect control layer includes one of Al-containing ternary nitride, Al-containing quaternary nitride, and a combination thereof.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: November 14, 2023
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Yung-Ling Lan, Chan-Chan Ling, Chi-Ming Tsai
  • Patent number: 11817018
    Abstract: The present invention is a message updating system for an electronic label. The system comprises a message updating device, wherein a controller thereof controls a power-supply transmission unit and a message-update transmission unit to respectively transmit a charging signal and a message-updating to the electronic label for charging the electronic label and updating label information of the electronic label. A detection device picks up the label information to generate label content information, transmits the label content information to the controller to make the controller compare the label content information with update comparison information, and generates an alert message if the label content information is different from the update comparison information. The present can charge the electronic label that is mounted on an article and update label information simultaneously while the article is being transported.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: November 14, 2023
    Assignee: Netronix, Inc.
    Inventors: Fang Ming Tsai, Jun Sheng Lin
  • Patent number: 11810826
    Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yip Loh, Yan-Ming Tsai, Hung-Hsu Chen, Chih-Wei Chang, Sheng-Hsuan Lin
  • Publication number: 20230341765
    Abstract: A method includes: providing a first design layout including a plurality of cells; updating a first cell of the plurality of cells using optical proximity correction to provide a first updated cell and a data set; and updating a second cell from remaining cells in the first design layout based on the data set and a model without involvement of optical proximity correction to provide a second updated cell, wherein the model includes hidden layers including nodes and is trained to obtaining converged values of the nodes of the hidden layers through providing a mapping of edge segments before lithography enhancement and edge segments after lithography enhancement using optical proximity correction, and wherein at least one of the providing, and updating is executed by one or more processors.
    Type: Application
    Filed: June 29, 2023
    Publication date: October 26, 2023
    Inventors: WEI-LIN CHU, HSIN-LUN TSENG, SHENG-WEN HUANG, CHIH-CHUNG HUANG, CHI-MING TSAI
  • Patent number: 11800102
    Abstract: Low-latency video coding methods and apparatuses include receiving input data associated with a current Intra slice composed of Coding Tree Units (CTU), where each CTU includes luma and chroma Coding Tree Blocks (CTBs), partitioning each CTB into non-overlapping pipeline units, and encoding or decoding the CTUs in the current Intra slices by performing processing of chroma pipeline units after beginning processing of luma pipeline units in at least one pipeline stage. Each of the pipeline units is processed by one pipeline stage after another pipeline stage, and different pipeline stages process different pipeline units simultaneously. The pipeline stage in the low-latency video coding methods and apparatuses simultaneously processes one luma pipeline unit and at least one previous chroma pipeline unit within one pipeline unit time interval.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: October 24, 2023
    Assignee: MEDIATEK INC.
    Inventors: Chia-Ming Tsai, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11784187
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment material layer is formed over the gate dielectric layer, an adhesion enhancement layer is formed on the first work function adjustment material layer, a mask layer including an antireflective organic material layer is formed on the adhesion enhancement layer, and the adhesion enhancement layer and the first work function adjustment material layer are patterned by using the mask layer as an etching mask. The adhesion enhancement layer has a higher adhesion strength to the antireflective organic material layer than the first work function adjustment material layer.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chandrashekhar Prakash Savant, Tien-Wei Yu, Chia-Ming Tsai
  • Publication number: 20230318310
    Abstract: The present invention provides a control system in which an energy-saving brushless micro-kinetic energy generating device is connected in parallel with a mains power supply device. The control system detects the actual power consumption of the load end, so that the control system of the invention can drive the switch according to the power consumption of the load end. An energy-saving brushless micro-kinetic energy generator or a mains power supply device is selected for power supply, so that users can achieve the effect of energy saving.
    Type: Application
    Filed: September 13, 2022
    Publication date: October 5, 2023
    Inventors: Chih-Ming Tseng, Jui-Ming Tsai
  • Publication number: 20230314953
    Abstract: Embodiments described herein relate to methods of printing features within a lithography environment. The methods include determining a mask pattern. The mask pattern includes auxiliary features to be provided with main features to a maskless lithography device in a lithography process. The auxiliary features are determined with a rule-based process flow or a lithography model process flow.
    Type: Application
    Filed: September 16, 2021
    Publication date: October 5, 2023
    Inventors: Chi-Ming TSAI, Thomas L. LAIDIG, Douglas Joseph VAN DEN BROEKE, Jang Fung CHEN