Abstract: A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region.

Abstract: An integrated circuit device includes a semiconductor substrate and a first transistor and a second transistor constructed in the semiconductor substrate. The first transistor has a first operating voltage higher than a second operating voltage of a second transistor. The first transistor includes a first drain structure, a first source structure, an isolation structure and a first gate structure. The first source structure includes a high voltage first-polarity well region, a first-polarity body region, a heavily doped first-polarity region, a second-polarity grade region and a heavily doped second-polarity region. The heavily doped second-polarity region is surrounded by the second-polarity grade region. The second-polarity grade region is surrounded by the first-polarity body region. The second transistor includes a second drain structure, a second source structure, a second gate structure and a first-polarity drift region.

Abstract: A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region.

Abstract: The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground.

Abstract: A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region includes a plurality of gaps formed therein. The non-continuous doped region further includes a second conductivity type complementary to the first conductivity type.

Abstract: A high voltage metal-oxide-semiconductor (HV MOS) device includes a substrate, a gate positioned on the substrate, a drain region formed in the substrate, a source region formed in the substrate, a first doped region formed in between the drain region and the source region, and a second doped region formed over a top of the first doped region or/and under a bottom of the first doped region. The drain region, the source region, and the second doped region include a first conductivity type, the first doped region includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary.

Abstract: A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region further includes a plurality of third doped regions, a plurality of gaps, and a plurality of fourth doped regions. The gaps and the third doped regions s are alternately arranged, and the fourth doped regions are formed in the gaps. The third doped regions include a second conductivity type complementary to the first conductivity type, and the fourth doped regions include the first conductivity type.

Abstract: A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region includes a plurality of gaps formed therein. The non-continuous doped region further includes a second conductivity type complementary to the first conductivity type.

Abstract: A HV MOSFET device includes a substrate, a deep well region, a source/body region, a drain region, a gate structure, and a first doped region. The deep well region includes a boundary site and a middle site. The source/body region is formed in the deep well region and defines a channel region. The first doped region is formed in the deep well region and disposed under the gate structure, and having the first conductivity type. There is a first ratio between a dopant dose of the first doped region and a dopant dose of the boundary site of the deep well region. There is a second ratio between a dopant dose of the first doped region and a dopant dose of the middle site of the deep well region. A percentage difference between the first ratio and the second ratio is smaller than or equal to 5%.

Abstract: A HV MOSFET device includes a substrate, a deep well region, a source/body region, a drain region, a gate structure, and a first doped region. The deep well region includes a boundary site and a middle site. The source/body region is formed in the deep well region and defines a channel region. The first doped region is formed in the deep well region and disposed under the gate structure, and having the first conductivity type. There is a first ratio between a dopant dose of the first doped region and a dopant dose of the boundary site of the deep well region. There is a second ratio between a dopant dose of the first doped region and a dopant dose of the middle site of the deep well region. A percentage difference between the first ratio and the second ratio is smaller than or equal to 5%.

Abstract: An integrated circuit device including: a first die, a first die bonding pad formed on the first die, a gold bump electrode formed on the first bonding pad, and a copper wire having a first end portion stitch bonded to the gold bump electrode; and a method of forming the integrated circuit device.

Abstract: The present invention provides a high-voltage semiconductor device including a deep well, a first doped region disposed in the deep well, a high-voltage well, a second doped region disposed in the high-voltage well, a first gate structure disposed on the high-voltage well between the second doped region and the first doped region, a doped channel region disposed in the high-voltage region and in contact with the second doped region and the deep well, and a third doped region disposed in the high-voltage well. The high-voltage well has a first conductive type, and the deep well, the first doped region, the second doped region, the doped channel region, and the third doped region have a second conductive type different from the first conductive type.

Abstract: A high voltage device is provided. The high voltage device includes a gate on a substrate, two source/drain regions in the substrate beside the gate, and a composite gate dielectric layer that includes at least two stacked continuous layers, extending from one side to another side of the gate. Wherein, the at least two stacked continuous layers is a combination of at least one thermal oxide layer and at least one chemical vapor deposited layer.

Abstract: An integrated circuit device includes a semiconductor substrate and a first transistor and a second transistor constructed in the semiconductor substrate. The first transistor has a first operating voltage higher than a second operating voltage of a second transistor. The first transistor includes a first drain structure, a first source structure, an isolation structure and a first gate structure. The first source structure includes a high voltage first-polarity well region, a first-polarity body region, a heavily doped first-polarity region, a second-polarity grade region and a heavily doped second-polarity region. The heavily doped second-polarity region is surrounded by the second-polarity grade region. The second-polarity grade region is surrounded by the first-polarity body region. The second transistor includes a second drain structure, a second source structure, a second gate structure and a first-polarity drift region.

Abstract: The present invention provides a high-voltage semiconductor device including a deep well, a first doped region disposed in the deep well, a high-voltage well, a second doped region disposed in the high-voltage well, a first gate structure disposed on the high-voltage well between the second doped region and the first doped region, a doped channel region disposed in the high-voltage region and in contact with the second doped region and the deep well, and a third doped region disposed in the high-voltage well. The high-voltage well has a first conductive type, and the deep well, the first doped region, the second doped region, the doped channel region, and the third doped region have a second conductive type different from the first conductive type.

Abstract: The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground.

Abstract: A socket terminal heat-dissipating mechanism is provided for use in an electronic device. The electronic device includes a frame and a casing. The socket terminal heat-dissipating mechanism includes a socket and an insulating layer. The socket is mounted in the frame of the electronic device, and includes a contact terminal. The insulating layer is arranged between the contact terminal and the casing of the electronic device, wherein heat energy is conducted from the contact terminal of the socket to the casing through the insulating layer, and passively dissipated away.

Abstract: A conductive winding structure, the fabricating method thereof, and the magnetic device having the same. The method for fabricating the conductive winding structure includes: (a) providing a mold with a plurality of extension portions and a plurality of protrusions, the plurality of extension portions are connected to each other as a continuous spiral structure, and the plurality of protrusions extend from the plurality of extension portions; (b) performing an electroforming procedure to form a conductive layer on partial surface of the mold; and (c) stripping the conductive layer from the mold, so as to obtain the conductive winding structure.

Abstract: A power supply device includes a mini projecting module, a power converting module and a signal transmission element. The power converting module includes a power input part, a power converting circuit and a power output part. The power converting circuit is used for converting the input voltage into a first output voltage and a second output voltage. The first output voltage and the second output voltage are respectively transmitted to an electronic device and the mini projecting module. The first output voltage is transmitted to the electronic device through the power output part. The signal transmission element is used for connecting the electronic device or an image signal source with the mini projecting module so that an image signal provided by the electronic device or the image signal source is transmitted to the mini projecting module through the signal transmission element.

Abstract: A socket terminal heat-dissipating mechanism is provided for use in an electronic device. The electronic device includes a frame and a casing. The socket terminal heat-dissipating mechanism includes a socket and an insulating layer. The socket is mounted in the frame of the electronic device, and includes a contact terminal. The insulating layer is arranged between the contact terminal and the casing of the electronic device, wherein heat energy is conducted from the contact terminal of the socket to the casing through the insulating layer, and passively dissipated away.