Abstract: A single side high voltage lateral diffused metal-oxide-semiconductor (LDMOS) transistor is disclosed. The drain side is low-voltage N-well with lower concentration to increase driving voltage while the source side is low-voltage P-well with higher concentration to increase the interior electric field such that the conductivity is improved and the threshold voltage is adjusted by high-voltage P-well with lower concentration.

Abstract: A method of fabricating a high power bipolar junction transistor. A P-type substrate having an N-type buried region is provided and a trench is formed within the substrate to expose the buried region. N-type ions are implanted and driven into the sidewall of the trench to form a sinker. Since the area and the depth of implantation are larger and deeper than that in prior art, the concentration of the sinker is more uniform and the diffusion range is easily controlled. An N-type epitaxial layer is then formed in the trench and an emitter, a base and their contacts are formed by conventional technique.

Abstract: A method for forming high-voltage semiconductor devices that have trench structure, substantially facilitating the integration of the high-voltage devices and the low-voltage devices, is disclosed. The method includes providing a semiconductor substrate, and forming a blocking layer on the substrate. The blocking layer and the substrate are defined and etched to form at least two trenches therein. Next, the substrate is firstly implanted using the blocking layer as a mask to form at least two drift regions. After refilling the trenches by a dielectric layer to form at least two dielectric regions in the substrate, a gate is then formed and patterned to form a gate region on the substrate, wherein the gate region covers the channel region and portions of the dielectric regions. Finally, secondly implanting the substrate is performed to form source/drain region using the gate region and the dielectric regions as a mask.

Abstract: A method of forming gate oxide layers. A first and a second poly-silicon gates are formed over a substrate. An amorphous silicon layer is formed on the first poly-silicon gate, followed by oxidizing the amorphous silicon layer and the second poly-silicon gate. A poly-silicon layer is formed on the gate oxide layers, devices with different capacitance are formed.

Abstract: A trench isolation structure for high voltage device is provided including a high voltage well, a low voltage well, and trench oxide. The high voltage well is formed first to be the deep junction isolation of isolation region. Next, the trench oxide isolation is formed overlying the high voltage well. Then, the low voltage well with higher concentration is formed underlying the trench oxide by using high energy implant. The isolation structure is a trench oxide(dielectric isolation)-junction isolation structure.

Abstract: A structure of high voltage semiconductor devices having N-well 1 and N-well 2 formed with two different doping densities acting as a gradient doping of a drift region. This structure results in a lift in its current drive capability and as well as in its breakdown voltage. The structure further comprises a buried spacer oxide, serving as a point of exertion for the edges of the buried gate electrode. And finally, since the gate electrode is formed by a trenching method, not only is the channel length increased with the placement of both the channel and drift regions changes in the to vertical direction, all of those contribute to a great reduction in the occupied chip area.

Abstract: The present invention provides a fabricating method of a high-voltage device. The invention provides N.sup.-- -type doped regions with properly low doping concentration in order to increase breakdown voltage. Field oxide layers are used as masks in a self-aligned ion implantation step to form N.sup.- -type doped drift regions with a higher doping concentration than the N.sup.-- -type doped regions. A recessed gate is formed so that the channel length is increased and the curvature of the electrical distribution lines on the edge of a drain region nearby a channel is decreased while the device is operated under high voltage.

Abstract: An improved method for simultaneously forming low voltage and high voltage devices is disclosed. The method includes using gradient doping to generate the gradient concentration in a semiconductor such that can tolerate higher threshold voltage. The device can get higher driving current by using gradient doping only in drain regions in metal-oxide-semiconductor field effect transistor (MOSFET). In addition, the invention can simultaneously generate higher current gain bipolar junction transistor (BJT) for applied integrated circuit. Further more, the invention can meet small layout rule of low voltage device and the only drain region to be operated in a high voltage device.

Abstract: A method for fabricating an improved structure of a high-bias device includes forming multiple doped wells between source/drain regions and a P-type substrate. The doped wells have an increasing order of dopant density from the P-type substrate for the P-type dopant or from a first N-type well for an N-type dopant. The doped multiple wells enclose the source/drain regions so that the source/drain regions do not directly contact with the substrate.

Abstract: A method for fabricating a high-bias device is provided. The method contains forming an N-type epitaxial silicon layer over a P-type substrate. At least a first stacked double well is formed in the epitaxial silicon layer at a region, where a field oxide (FOX) structure is to be formed. A second stacked double well is formed in the epitaxial silicon layer at a region, where a source region is to be formed inside. A FOX structure is formed on the first stacked double well. A gate oxide layer is formed on the epitaxial silicon layer. A conductive gate layer is formed over the substrate to cover a region extending from a portion of the FOX structure to a portion of the second stacked double well. A source region is formed in the second stacked double well with the second-type dopant. A drain region is formed in the epitaxial silicon layer at the opposite side of the FOX layer.

Abstract: A method of forming a high-voltage device is provided. A substrate with a first electrical type is provided. A first doped region with a second electrical type is formed in a portion of the substrate. A first field oxide layer and a second field oxide layer are formed on the first doped region and on the substrate near the first doped region. A second doped region with the second electrical type is formed in the substrate between the first field oxide layer and the second field oxide layer. Doping concentration of the second doped region is higher than of the first doped region. A third doped region with the first electrical type is formed in the substrate near the second field oxide layer. Doping concentration of the third doped region and doping concentration of the first doped region are the same. A source region is formed within the top portion of the first doped region near the first field oxide layer.

Abstract: A resistor on a semiconductor wafer comprising a silicon substrate, a first doped layer in a predetermined area on the silicon substrate, a second doped layer within a predetermined area of the first doped layer, a dielectric layer above the first and second doped layers on the silicon substrate, a passivation layer on the dielectric layer, and a conducting layer between the dielectric layer and the passivation layer. The silicon substrate contains dopants that characterize it as an n-type (or p-type) semiconductor. The first doped layer functioning as a resistor layer is a p-type (or n-type) semiconductor and forms a first pn-junction at its interface with the silicon substrate to prevent electrical leakage. The second doped layer is a n-type (p-type) semiconductor and forms a second pn-junction at its interface with the first doped layer that prevents electrical leakage. The passivation layer has a plurality of charges at fixed positions.

Abstract: A method for fabricating high-voltage semiconductor devices is disclosed, in which a P-well and a N-well are first formed over the substrate, where a plurality of P-wells and N-wells used as isolation regions and drift regions are further formed therein. More shallot P-type and N-type regions are subsequently formed in the drift regions and isolation regions, so as to increase the breakdown voltage and enhance the current-driving performance. In addition, a deepened isolation doping, can also increase the latch up capability, resulting in less area required for fabricating a device.

Abstract: A method for fabricating a high-bias device compatible with a low-bias device is provided. The method of the invention includes using a doped well as a drift region of the high-bias device so that the drift region can be formed simultaneously when a well for a low-bias device is formed. The method of the invention also fabricates the high-bias device and the low-bias device simultaneously, using a commonly used photomask. Several ion implantation processes are also performed simultaneously. There is no need of some extra fabrication of photomasks and ion implantation processes separately used for forming the high-bias device.