Patents by Inventor Ming-Tsung Tung
Ming-Tsung Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8026549Abstract: A semiconductor device and an IC chip are described. The deep N-well region is configured in a substrate. The P-well region surrounds a periphery of the deep N-well region. The gate structure is disposed on the substrate of the deep N-well region. The P-body region is configured in the deep N-well region at one side of the gate structure. The first N-type doped region is configured in the P-body region. The second N-type doped region is configured pin the deep N-well region at the other side of the gate structure. The first isolation structure is disposed between the gate structure and the second N-type doped region. The N-type isolation ring is configured in the deep N-well region and corresponding to an edge of the deep N-well region, wherein a doping concentration of the N-type isolation ring is higher than that of the deep N-well region.Type: GrantFiled: October 31, 2008Date of Patent: September 27, 2011Assignee: United Microelectronics Corp.Inventors: Chin-Lung Chen, Chun-Ching Yu, Jung-Ching Chen, Ming-Tsung Tung
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Patent number: 7868372Abstract: A method for forming a depletion-mode single-poly electrically erasable programmable read-only memory (EEPROM) cell is provided. The method includes providing a substrate having a floating region and a control region. Then, an isolation deep well and a deep well are formed in the floating region and the control region of the substrate respectively. A well region is formed in the isolation deep well simultaneously with forming an isolation well region between the isolation deep well and the deep well in the substrate. A depletion doped region and a cell implant region are formed at the well region of the substrate and the deep well of the substrate respectively. A floating gate structure is formed across over the floating region and the control region. An implantation process is performed to form a source/drain region and a heavily doped region in the depletion doped region and the cell implant region respectively.Type: GrantFiled: July 10, 2006Date of Patent: January 11, 2011Assignee: United Microelectronics Corp.Inventors: Jung-Ching Chen, Ming-Tsung Tung
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Publication number: 20100109081Abstract: A semiconductor device and an IC chip are described. The deep N-well region is configured in a substrate. The P-well region surrounds a periphery of the deep N-well region. The gate structure is disposed on the substrate of the deep N-well region. The P-body region is configured in the deep N-well region at one side of the gate structure. The first N-type doped region is configured in the P-body region. The second N-type doped region is configured pin the deep N-well region at the other side of the gate structure. The first isolation structure is disposed between the gate structure and the second N-type doped region. The N-type isolation ring is configured in the deep N-well region and corresponding to an edge of the deep N-well region, wherein a doping concentration of the N-type isolation ring is higher than that of the deep N-well region.Type: ApplicationFiled: October 31, 2008Publication date: May 6, 2010Applicant: United Microelectronics Corp.Inventors: Chin-Lung Chen, Chun-Ching Yu, Jung-Ching Chen, Ming-Tsung Tung
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Publication number: 20090184368Abstract: An IC chip, including a switch LDMOS device and an analog LDMOS device, is configured on a substrate having a first conductive type. Components of the two LDMOS devices respectively include two gate conductive layers configured on two first active regions of the substrate. A common source contact region having a second conductive type is configured in a second active region, which is configured between the two first active regions. An isolation structure is included for isolating the second active region and the first active regions. The isolation structure between the first active regions and the second active region has a length “A” extending along a longitudinal direction of a channel under each gate conductive layer, and each gate conductive layer on each first active region has a length “L” extending along the longitudinal direction of the channel, the two LDMOS devices have different A/L values.Type: ApplicationFiled: January 23, 2008Publication date: July 23, 2009Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chin-Hung Liu, Chin-Lung Chen, Ming-Tsung Tung, Wen-Kuo Li
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Patent number: 7560774Abstract: An IC chip, including a switch LDMOS device and an analog LDMOS device, is configured on a substrate having a first conductive type. Components of the two LDMOS devices respectively include two gate conductive layers configured on two first active regions of the substrate. A common source contact region having a second conductive type is configured in a second active region, which is configured between the two first active regions. An isolation structure is included for isolating the second active region and the first active regions. The isolation structure between the first active regions and the second active region has a length “A” extending along a longitudinal direction of a channel under each gate conductive layer, and each gate conductive layer on each first active region has a length “L” extending along the longitudinal direction of the channel, the two LDMOS devices have different A/L values.Type: GrantFiled: January 23, 2008Date of Patent: July 14, 2009Assignee: United Microelectronics Corp.Inventors: Chin-Hung Liu, Chin-Lung Chen, Ming-Tsung Tung, Wen-Kuo Li
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Publication number: 20080007998Abstract: A method for forming a depletion-mode single-poly electrically erasable programmable read-only memory (EEPROM) cell is provided. The method comprises providing a substrate having a floating region and a control region. Then, an isolation deep well and a deep well are formed in the floating region and the control region of the substrate respectively. A well region is formed in the isolation deep well simultaneously with forming an isolation well region between the isolation deep well and the deep well in the substrate. A depletion doped region and a cell implant region are formed at the well region of the substrate and the deep well of the substrate respectively. A floating gate structure is formed across over the floating region and the control region. An implantation process is performed to form a source/drain region and a heavily doped region in the depletion doped region and the cell implant region respectively.Type: ApplicationFiled: July 10, 2006Publication date: January 10, 2008Inventors: Jung-Ching Chen, Ming-Tsung Tung
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Publication number: 20070273001Abstract: A system-on-chip semiconductor structure. The system-on-chip semiconductor structure comprises a substrate, a low voltage device, a middle voltage device, at least one high voltage device and a plurality of isolation structures. The substrate has a low voltage circuit region and a high voltage circuit region. The low voltage device is located on the low voltage circuit region of the substrate. The middle voltage device is located on the low voltage circuit region of the substrate. The high voltage device is located on the high voltage circuit region of the substrate. The isolation structures are located in the substrate for isolating the low voltage device, the middle voltage device and the high voltage device from each other.Type: ApplicationFiled: May 24, 2006Publication date: November 29, 2007Inventors: Jung-Ching Chen, Ming-Tsung Tung
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Publication number: 20070254417Abstract: A semiconductor device having a capacitor is provided. The semiconductor device includes a substrate, a capacitor and a metal-oxide-semiconductor (MOS) transistor. The MOS transistor is located in a MOS transistor region of the substrate, and the MOS transistor region has a first bottom diffusion region. The capacitor is located in a capacitor region of the substrate and consisted of a second bottom diffusion region located in the substrate, a first dielectric layer located over the second bottom diffusion region, a bottom conductive layer located over the first dielectric layer, a second dielectric layer located over the bottom conductive layer, and a top conductive layer located over the second dielectric layer. The first bottom diffusion region and the second bottom diffusion region are different conductive type.Type: ApplicationFiled: July 13, 2007Publication date: November 1, 2007Applicant: United Microelectronics Corp.Inventors: Jung-Ching Chen, Chin-Hung Liu, Chien-Ming Lin, Ming-Tsung Tung
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Patent number: 7256095Abstract: A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate electrode; etching a thickness of the gate dielectric layer not covered by the gate electrode; stripping the resist mask; forming a salicide block resist mask covering the gate electrode and a portions of the remaining gate dielectric layer; etching away the remaining gate dielectric layer not covered by the salicide block resist mask, thereby exposing the substrate and forming a salicide block lug portions on two opposite sides of the gate electrode; and making a metal layer react with the substrate, thereby forming a salicide layer that is kept a distance “d” away from the gate electrode.Type: GrantFiled: August 31, 2006Date of Patent: August 14, 2007Assignee: United Microelectronics Corp.Inventors: Chien-Ming Lin, Ming-Tsung Tung, Chin-Hung Liu
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Patent number: 7244975Abstract: A high-voltage device structure includes a high-voltage device disposed on a semiconductor substrate. The semiconductor includes an active region and an isolation region, and the high-voltage device is disposed in the active region. The high-voltage device structure includes a source diffusion region of a first conductive type, a drain region of the first conductive type, and a gate longer than the source diffusion region and the drain diffusion region so as to form spare regions on both sides of the gate. The isolation region is outside the active region and surrounds the active region. In the isolation region, an isolation ion implantation region of a second conductive type and an extended ion implantation region are disposed to prevent parasitic current from being generating between the source diffusion region and the drain diffusion region.Type: GrantFiled: July 5, 2005Date of Patent: July 17, 2007Assignee: United Microelectronics Corp.Inventors: Anchor Chen, Chih-Hung Lin, Hwi-Huang Chen, Jih-Wei Liou, Chin-Hung Liu, Ming-Tsung Tung, Chien-Ming Lin, Jung-Ching Chen
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Publication number: 20070141776Abstract: A semiconductor device having a capacitor is provided. The semiconductor device includes a substrate, a capacitor and a metal-oxide-semiconductor (MOS) transistor. The MOS transistor is located in a MOS transistor region of the substrate, and the MOS transistor region has a first bottom diffusion region. The capacitor is located in a capacitor region of the substrate and consisted of a second bottom diffusion region located in the substrate, a first dielectric layer located over the second bottom diffusion region, a bottom conductive layer located over the first dielectric layer, a second dielectric layer located over the bottom conductive layer, and a top conductive layer located over the second dielectric layer. The first bottom diffusion region and the second bottom diffusion region are different conductive type.Type: ApplicationFiled: December 19, 2005Publication date: June 21, 2007Inventors: Jung-Ching Chen, Chin-Hung Liu, Chien-Ming Lin, Ming-Tsung Tung
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Publication number: 20070018258Abstract: A high-voltage device structure includes a high-voltage device disposed on a semiconductor substrate. The semiconductor includes an active region and an isolation region, and the high-voltage device is disposed in the active region. The high-voltage device structure includes a source diffusion region of a first conductive type, a drain region of the first conductive type, and a gate longer than the source diffusion region and the drain diffusion region so as to form spare regions on both sides of the gate. The isolation region is outside the active region and surrounds the active region. In the isolation region, an isolation ion implantation region of a second conductive type and an extended ion implantation region are disposed to prevent parasitic current from being generating between the source diffusion region and the drain diffusion region.Type: ApplicationFiled: July 5, 2005Publication date: January 25, 2007Inventors: Anchor Chen, Chih-Hung Lin, Hwi-Huang Chen, Jih-Wei Liou, Chin-Hung Liu, Ming-Tsung Tung, Chien-Ming Lin, Jung-Ching CHEN
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Publication number: 20060292803Abstract: A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate electrode; etching a thickness of the gate dielectric layer not covered by the gate electrode; stripping the resist mask; forming a salicide block resist mask covering the gate electrode and a portions of the remaining gate dielectric layer; etching away the remaining gate dielectric layer not covered by the salicide block resist mask, thereby exposing the substrate and forming a salicide block lug portions on two opposite sides of the gate electrode; and making a metal layer react with the substrate, thereby forming a salicide layer that is kept a distance “d” away from the gate electrode.Type: ApplicationFiled: August 31, 2006Publication date: December 28, 2006Inventors: Chien-Ming Lin, Ming-Tsung Tung, Chin-Hung Liu
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Publication number: 20060270162Abstract: A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate electrode; etching a thickness of the gate dielectric layer not covered by the gate electrode; stripping the resist mask; forming a salicide block resist mask covering the gate electrode and a portions of the remaining gate dielectric layer; etching away the remaining gate dielectric layer not covered by the salicide block resist mask, thereby exposing the substrate and forming a salicide block lug portions on two opposite sides of the gate electrode; and making a metal layer react with the substrate, thereby forming a salicide layer that is kept a distance “d” away from the gate electrode.Type: ApplicationFiled: January 23, 2006Publication date: November 30, 2006Inventors: Chien-Ming Lin, Ming-Tsung Tung, Chin-Hung Liu
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Patent number: 7118954Abstract: A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate electrode; etching a thickness of the gate dielectric layer not covered by the gate electrode; stripping the resist mask; forming a salicide block resist mask covering the gate electrode and a portions of the remaining gate dielectric layer; etching away the remaining gate dielectric layer not covered by the salicide block resist mask, thereby exposing the substrate and forming a salicide block lug portions on two opposite sides of the gate electrode; and making a metal layer react with the substrate, thereby forming a salicide layer that is kept a distance “d” away from the gate electrode.Type: GrantFiled: May 26, 2005Date of Patent: October 10, 2006Assignee: United Microelectronics Corp.Inventors: Chien-Ming Lin, Ming-Tsung Tung, Chin-Hung Liu
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Publication number: 20060211232Abstract: A method for manufacturing gold bumps includes providing a substrate including a patterned protective layer, which exposes at least a bonding pad, on a surface, covering a photo resist on the surface of the substrate, performing a photolithography process to pattern the photo resist for exposing a portion of the protective layer and the bonding pad, removing a portion of the protective layer, removing the photo resist, and performing a gold bumping process. The resulting thickness of the protective layer covering the bonding pad is smaller than the resulting thickness of the protective layer covering the substrate.Type: ApplicationFiled: March 16, 2005Publication date: September 21, 2006Inventors: Mei-Jen Liu, Yu-Ting Lai, Kuang-Shin Lee, Ming-Tsung Tung
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Patent number: 6429077Abstract: The present invention provides a method of forming a lateral diffused metal-oxide semiconductor (LD MOS) transistor on a semiconductor wafer. An ion implantation process is performed on a predetermined area of the silicon substrate so as to form a p-well adjacent to an n-well. An insulation layer is then formed on a predetermined area of the n-well. A gate layer is formed on a portion of the p-well and the n-well, and one side of the gate layer is positioned on the surface of the insulation layer. Finally, an ion implantation process is performed to form two n-type doped regions on the p-well and the n-well. The two doped regions are used as the source and the drain of the LD MOS transistor.Type: GrantFiled: December 2, 1999Date of Patent: August 6, 2002Assignee: United Microelectronics Corp.Inventor: Ming-Tsung Tung
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Patent number: 6392274Abstract: A method for fabricating an HVMOS transistor that can reduce snapback is disclosed. The semiconductor wafer comprises an N-type silicon substrate, and a P-type epitaxial layer formed on the surface of the silicon substrate. The HVMOS transistor comprises a first P-well region formed within the epitaxial layer, a second P-well region formed within the first P-well region a source region formed within the second P-well region, an N-drain region formed in the epitaxial layer, a gate, and an N-type diffused region formed both in the epitaxial layer and in the silicon substrate. The diffused region is under the first P-well region and overlaps the first P-well region.Type: GrantFiled: April 4, 2000Date of Patent: May 21, 2002Assignee: United Microelectronics Corp.Inventor: Ming-Tsung Tung
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Patent number: 6391698Abstract: The present invention provides a method for forming a transistor with a gradient doped source/drain. The method comprises the following steps. First, two first N-wells are formed in a substrate and the first N-wells are separated in both sides of the substrate. The, two second N-wells are formed in the substrate and the second N-wells overlie the first N-wells. An implanting concentration of first N-wells is smaller than an implanting concentration of second N-wells. Next, a field oxide region is formed in the substrate between the first N-wells and the field oxide region overlies on a portion of second N-wells. Thereafter, portion of the field oxide region and the substrate are removed to form a trench n the substrate, wherein the remaining field oxide region overlies on the second N-wells. Next, a gate oxide layer is formed on a bottom surface and sidewall of the trench. Then, a polysilicon gate is formed on the substrate.Type: GrantFiled: February 26, 1999Date of Patent: May 21, 2002Assignee: United Microelectronics Corp.Inventor: Ming-Tsung Tung
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Patent number: 6376296Abstract: A high-voltage device. A substrate has a first conductive type. A first well region with the first conductive type is located in the substrate. A second well region with the second conductive type is located in the substrate but is isolated from the first well region. Several field oxide layers are located on a surface of the second well region. A shallow trench isolation is located between the field oxide layers in the second well region. A first doped region with the second conductive type is located beneath the field oxide layers. A second doped region with the first conductive type is located beneath the shallow trench isolation in the second well region. A third well region with the first conductive type is located in the first well region and expands from a surface of the first well region into the first well region. A gate structure is positioned on the substrate between the first and the second well regions and covers a portion of the first, the third well regions and the field oxide layers.Type: GrantFiled: February 23, 2001Date of Patent: April 23, 2002Assignee: United Microelectronics Corp.Inventor: Ming-Tsung Tung