Abstract: A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.

Abstract: A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor. The at least one processor may be configured to transmit a first synchronization sequence to a secondary device, detect a second synchronization sequence transmitted by the secondary device, the second synchronization sequence differing from the first synchronization sequence, and after detection of the second synchronization sequence, initiate a training stage, the train stage comprising exchanging training frames with the secondary device. The at least one processor may be further configured to enter a data mode for data transmissions after completion of the training stage, the data transmissions being distinct from the training frames. In the data mode, data may be forward error correction encoded and then scrambled.

Abstract: A semiconductor structure has an integrated circuit component, a conductive contact pad, a seal ring structure, a conductive via, a ring barrier, and a mold material. The conductive contact pad is disposed on and electrically connected with the integrated circuit component. The seal ring structure is disposed on the integrated circuit component and surrounding the conductive contact pad. The conductive via is disposed on and electrically connected with the conductive contact pad. The ring barrier is disposed on the seal ring structure. The ring barrier surrounds the conductive via. The mold material covers side surfaces of the integrated circuit component. A semiconductor manufacturing process is also provided.

Abstract: A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

Abstract: A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.

Abstract: A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor circuit. The at least one processor circuit may be configured to transmit a first synchronization sequence to a secondary device and to subsequently detect a second synchronization sequence, different than the first, transmitted by the secondary device. The synchronization sequences may be pseudo-noise sequences that have strong autocorrelation characteristics. The at least one processor circuit may be configured to wait a predetermined amount of time after completing the detection of the second synchronization sequence, and then may initiate a training stage. The training stage may include exchanging scrambler states of additive scramblers used by the primary and secondary devices. The at least one processor circuit may be configured to enter a data mode upon completion of training. In the data mode, data is forward error correction encoded and then scrambled.

Abstract: A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

Abstract: An optical sensing system is disclosed. The optical sensing system includes a printed circuit board (PCB), a supporter and an optical sensor. The PCB includes a top surface, a bottom surface and a through cavity, wherein the through cavity extends downwardly from the top surface to the bottom surface. The supporter has a top surface and a bottom surface. The optical sensor is bonded and coupled to the top surface of the supporter, wherein the optical sensor includes a primary optic structure. Wherein the supporter is flipped over and bonded to the PCB with the top surface facing the through cavity, so that the optical sensor is coupled to the PCB and at least partially extends to the through cavity. Associated electronic devices are also disclosed.

Abstract: An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.

Abstract: A system to implement a communication line coding scheme using a non-complex bit-to-symbol mapping, a forward error correction (FEC) coding, and an additive bit scrambler after the FEC at the PHY layer is provided. The system may be a part of or implemented by an automobile component. The system may be a PHY device configured to convert data from the MAC layer into 2D-PAM3 symbols that are transmitted across a communication link at a predetermined transmission rate, such as to be compliant with a communication standard. The PHY device may select characteristics of the conversion, such as the FEC coded symbol, based on the target transmission rate. The PHY device may include a transceiver, and may convert the data from MAC layer to PHY layer and back.

Abstract: A system to implement a communication line coding scheme using a non-complex bit-to-symbol mapping, a forward error correction (FEC) coding, and an additive bit scrambler after the FEC at the PHY layer is provided. The system may be a part of or implemented by an automobile component. The system may be a PHY device configured to convert data from the MAC layer into 2D-PAM3 symbols that are transmitted across a communication link at a predetermined transmission rate, such as to be compliant with a communication standard. The PHY device may select characteristics of the conversion, such as the FEC coded symbol, based on the target transmission rate. The PHY device may include a transceiver, and may convert the data from MAC layer to PHY layer and back.

Abstract: A method of manufacturing a semiconductor structure include: providing a die including a die pad disposed over the die; disposing a conductive member over the die pad of the die; forming a molding surrounding the die and the conductive member; disposing a dielectric layer over the molding, the die and the conductive member; and forming an interconnect structure including a land portion and a plurality of via portions. The land portion is disposed over the dielectric layer, the plurality of via portions are disposed over the conductive member and protruded from the land portion to the conductive member through the dielectric layer, and each of the plurality of via portions at least partially contacts with the conductive member.

Abstract: A semiconductor device includes a first molding layer; a second molding layer formed over the first molding layer; a first conductive coil including a first portion continuously formed in the first molding layer and a second portion continuously formed in the second molding layer, wherein the first and the second portions are laterally displaced from each other; and a second conductive coil formed in the second molding layer, wherein the second conductive coil is interweaved with the second portion of the first conductive coil in the second molding layer.

Abstract: A light-emitting device is provided. The light-emitting device comprises The light-emitting device comprises a light-emitting stack comprising a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer; and a third semiconductor layer on the light-emitting stack and comprising a first sub-layer, a second sub-layer and a roughened surface, wherein the first sub-layer has the same composition as that of the second sub-layer, and the second sub-layer is farther from the light-emitting stack than the first sub-layer; wherein the first sub-layer and the second sub-layer each comprises a Group III element and a Group V element, and an atomic ratio of the Group III element to the Group V element of the first sub-layer is less than an atomic ratio of the Group III element to the Group V element of the second sub-layer.

Abstract: A semiconductor structure has an integrated circuit component, a conductive contact pad, a seal ring structure, a conductive via, a ring barrier, and a mold material. The conductive contact pad is disposed on and electrically connected with the integrated circuit component. The seal ring structure is disposed on the integrated circuit component and surrounding the conductive contact pad. The conductive via is disposed on and electrically connected with the conductive contact pad. The ring barrier is disposed on the seal ring structure. The ring barrier surrounds the conductive via. The mold material covers side surfaces of the integrated circuit component. A semiconductor manufacturing process is also provided.

Abstract: A conductive terminal on an integrated circuit is provided. The conductive terminal includes a conductive pad, a dielectric layer, and a conductive via. The conductive pad is disposed on and electrically to the integrated circuit. The dielectric layer covers the integrated circuit and the conductive pad, the dielectric layer includes a plurality of contact openings arranged in array, and the conductive pad is partially exposed by the contact openings. The conductive via is disposed on the dielectric layer and electrically connected to the conductive pad through the contact openings. The conductive via includes a plurality of convex portions arranged in array. The convex portions are distributed on a top surface of the conductive via, and the convex portions are corresponding to the contact openings.

Abstract: A conductive terminal on an integrated circuit is provided. The conductive terminal includes a conductive pad, a dielectric layer, and a conductive via. The conductive pad is disposed on and electrically to the integrated circuit. The dielectric layer covers the integrated circuit and the conductive pad, the dielectric layer includes a plurality of contact openings arranged in array, and the conductive pad is partially exposed by the contact openings. The conductive via is disposed on the dielectric layer and electrically connected to the conductive pad through the contact openings. The conductive via includes a plurality of convex portions arranged in array. The convex portions are distributed on a top surface of the conductive via, and the convex portions are corresponding to the contact openings.

Abstract: A light-emitting device is provided. The light-emitting device comprises a light-emitting stack comprising a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer. The light-emitting device further comprises a third semiconductor layer on the light-emitting stack and comprising a first sub-layer, a second sub-layer and a roughened surface, wherein the first sub-layer has the same composition as that of the second sub-layer, and the composition of the first sub-layer is with a different atomic ratio from that of the second sub-layer. A method for manufacturing the light-emitting device is also provided.

Abstract: A system to implement a communication line coding scheme using a non-complex bit-to-symbol mapping, a forward error correction (FEC) coding, and an additive bit scrambler after the FEC at the PHY layer is provided. The system may be a part of or implemented by an automobile component. The system may be a PHY device configured to convert data from the MAC layer into 2D-PAM3 symbols that are transmitted across a communication link at a predetermined transmission rate, such as to be compliant with a communication standard. The PHY device may select characteristics of the conversion, such as the FEC coded symbol, based on the target transmission rate. The PHY device may include a transceiver, and may convert the data from MAC layer to PHY layer and back.

Abstract: An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.