Patents by Inventor Ming-Tung Lee
Ming-Tung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9302904Abstract: A method of fabricating an integrated semiconductor device, comprising: providing a substrate having a first region and a second region; and forming a semiconductor unit on the first region and forming a micro electro mechanical system (MEMS) unit on the second region in one process.Type: GrantFiled: September 25, 2014Date of Patent: April 5, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsueh-I Huang, Ming-Tung Lee, Shuo-Lun Tu
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Patent number: 9202862Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first well, a first heavily doping region, a field oxide, a first dielectric layer, and a conductive layer. The first well is disposed on the substrate, and the first heavily doping region is disposed in the first well. The field oxide is disposed on the first well and adjacent to the first heavily doping region. The first dielectric layer is disposed on the field oxide and covering the field oxide. The conductive layer is disposed on the first dielectric layer. The first well and the first heavily doping region have a first type doping.Type: GrantFiled: March 14, 2014Date of Patent: December 1, 2015Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ming-Tung Lee, Cheng-Chi Lin, Chih-Chia Hsu, Chien-Chung Chen, Shih-Chin Lien, Shyi-Yuan Wu
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Publication number: 20150263085Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first well, a first heavily doping region, a field oxide, a first dielectric layer, and a conductive layer. The first well is disposed on the substrate, and the first heavily doping region is disposed in the first well. The field oxide is disposed on the first well and adjacent to the first heavily doping region. The first dielectric layer is disposed on the field oxide and covering the field oxide. The conductive layer is disposed on the first dielectric layer. The first well and the first heavily doping region have a first type doping.Type: ApplicationFiled: March 14, 2014Publication date: September 17, 2015Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ming-Tung Lee, Cheng-Chi Lin, Chih-Chia Hsu, Chien-Chung Chen, Shih-Chin Lien, Shyi-Yuan Wu
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Publication number: 20150044808Abstract: A method of fabricating an integrated semiconductor device, comprising: providing a substrate having a first region and a second region; and forming a semiconductor unit on the first region and forming a micro electro mechanical system (MEMS) unit on the second region in one process.Type: ApplicationFiled: September 25, 2014Publication date: February 12, 2015Inventors: Hsueh-I Huang, Ming-Tung Lee, Shuo-Lun Tu
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Patent number: 8940609Abstract: A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region.Type: GrantFiled: June 18, 2014Date of Patent: January 27, 2015Assignee: Macronix International Co., Ltd.Inventors: Chien-Chung Chen, Ming-Tung Lee, Shih-Chin Lien, Shyi-Yuan Wu
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Patent number: 8928095Abstract: A semiconductor device having a well, a p well implant bounded at least in part within a substrate by the well, a conductive layer disposed on the substrate, a high voltage n? (HVN?) doped well implanted in the p well implant, a high voltage p doped (HVPD) well implanted in the p well implant, and a drain n? well and a source n? well disposed in the HVN? doped well and HVPD well, respectively, is provided. A method of fabricating the semiconductor device is also provided. In certain embodiments, the method of fabricating the semiconductor device is characterized by implanting the HVN? ions at a first tilt angle and/or implanting the HVPD ions at a second tilt angle.Type: GrantFiled: August 16, 2013Date of Patent: January 6, 2015Assignee: Macronix International Co., Ltd.Inventors: Chien-Chung Chen, Ming-Tung Lee, Yin-Fu Huang, Shih-Chin Lien, Shyi-Yuan Wu
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Patent number: 8897470Abstract: A method of fabricating an integrated semiconductor device, comprising: providing a substrate having a first region and a second region; and forming a semiconductor unit on the first region and forming a micro electro mechanical system (MEMS) unit on the second region in one process.Type: GrantFiled: July 31, 2009Date of Patent: November 25, 2014Assignee: Macronix International Co., Ltd.Inventors: Hsueh-I Huang, Ming-Tung Lee, Shuo-Lun Tu
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Publication number: 20140302654Abstract: A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region.Type: ApplicationFiled: June 18, 2014Publication date: October 9, 2014Inventors: Chien-Chung Chen, Ming-Tung Lee, Shih-Chin Lien, Shyi-Yuan Wu
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Publication number: 20140264599Abstract: A semiconductor device having a well, a p well implant bounded at least in part within a substrate by the well, a conductive layer disposed on the substrate, a high voltage n? (HVN?) doped well implanted in the p well implant, a high voltage p doped (HVPD) well implanted in the p well implant, and a drain n? well and a source n? well disposed in the HVN? doped well and HVPD well, respectively, is provided. A method of fabricating the semiconductor device is also provided. In certain embodiments, the method of fabricating the semiconductor device is characterized by implanting the HVN? ions at a first tilt angle and/or implanting the HVPD ions at a second tilt angle.Type: ApplicationFiled: August 16, 2013Publication date: September 18, 2014Applicant: Macronix International Co. Ltd.Inventors: Chien-Chung Chen, Ming-Tung Lee, Yin-Fu Huang, Shin-Chin Lien, Shyi-Yuan Wu
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Patent number: 8829615Abstract: A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region.Type: GrantFiled: September 2, 2011Date of Patent: September 9, 2014Assignee: Macronix International Co., Ltd.Inventors: Chien-Chung Chen, Ming-Tung Lee, Shih-Chin Lien, Shyi-Yuan Wu
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Patent number: 8581339Abstract: A bipolar junction transistor and a manufacturing method for the same are provided. The bipolar junction transistor includes a well region, an emitter electrode, a base electrode, a collector electrode, and a conductive layer. The emitter electrode, the base electrode and the collector electrode are separated from each other by the well region. The conductive layer is on the well region between the base electrode and the collector electrode.Type: GrantFiled: August 8, 2011Date of Patent: November 12, 2013Assignee: Macronix International Co., Ltd.Inventors: Chin-Wei Chang, Ching-Lin Chan, Chin-Shien Lu, Ming-Tung Lee, Shuo-Lun Tu
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Publication number: 20130285136Abstract: An apparatus of and method for making enhanced Schottky diodes having p-body regions operable to pinch a current flow path in a high-voltage n-well region and field plate structures operable to distribute an electric potential of the Schottky diode allow for a device with enhanced breakdown voltage properties. N-well regions implanted into the substrate over a p-type epitaxial layer may act as an anode of the Schottky diode and n-type well regions implanted in the high-voltage n-well regions may act as cathodes of the Schottky diode. The Schottky diode may also be used as a low-side mosfet structure device.Type: ApplicationFiled: April 25, 2012Publication date: October 31, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chin-Hsien LU, Shuo-Lun TU, Chin-Wei CHANG, Ching-Lin CHAN, Ming-Tung LEE
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Publication number: 20130056825Abstract: A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region.Type: ApplicationFiled: September 2, 2011Publication date: March 7, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chien-Chung Chen, Ming-Tung Lee, Shih-Chin Lien, Shyi-Yuan Wu
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Publication number: 20130037914Abstract: A bipolar junction transistor and a manufacturing method for the same are provided. The bipolar junction transistor includes a well region, an emitter electrode, a base electrode, a collector electrode, and a conductive layer. The emitter electrode, the base electrode and the collector electrode are separated from each other by the well region. The conductive layer is on the well region between the base electrode and the collector electrode.Type: ApplicationFiled: August 8, 2011Publication date: February 14, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chin-Wei Chang, Ching-Lin Chan, Chin-Shien Lu, Ming-Tung Lee, Shuo-Lun Tu
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Patent number: 8357547Abstract: A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.Type: GrantFiled: June 29, 2012Date of Patent: January 22, 2013Assignee: Macronix International Co., Ltd.Inventors: Ming-Tung Lee, Shih-Chin Lien, Chia-Huan Chang
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Patent number: 8354716Abstract: A semiconductor device for use in a relatively high voltage application that comprises a substrate, a first n-type well region in the substrate to serve as a high voltage n-well (HVNW) for the semiconductor device, a pair of second n-type well regions in the first n-type well region, a p-type region in the first n-type well region between the second n-type well regions, a pair of conductive regions on the substrate between the second n-type well regions, and a number of n-type regions to serve as n-type buried layers (NBLs) for the semiconductor device, wherein the NBLs are located below the first n-type region and dispersed in the substrate.Type: GrantFiled: July 2, 2010Date of Patent: January 15, 2013Assignee: Macronix International Co., Ltd.Inventors: Hsueh I Huang, Ming-Tung Lee, Shyi-Yuan Wu
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Publication number: 20120270350Abstract: A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.Type: ApplicationFiled: June 29, 2012Publication date: October 25, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ming-Tung Lee, Shih-Chin Lien, Chia-Huan Chang
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Patent number: 8227877Abstract: A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.Type: GrantFiled: July 14, 2010Date of Patent: July 24, 2012Assignee: Macronix International Co., Ltd.Inventors: Ming-Tung Lee, Shih-Chin Lien, Chia-Huan Chang
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Publication number: 20120037989Abstract: LDMOS devices having a single-strip contact pad in the source region, and related methods of manufacturing are disclosed. The LDMOS may comprise a first well lightly doped with a first dopant and formed into a portion of a substrate, the first well having a drain region at its surface heavily doped with the first dopant, and a second well lightly doped with a second dopant formed in another portion of the substrate, the second well having a source region at its surface comprising first portions heavily doped with the first dopant directly adjacent second portions heavily doped with the second dopant. Also, the LDMOS device may comprise a field oxide at the upper surface of the substrate between the source and drain regions, and contacting the first well but separated from the second well, and a gate formed partially over the field oxide and partially over the source region.Type: ApplicationFiled: August 16, 2010Publication date: February 16, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsueh-I Huang, Shuo-Lun Tu, Ming-Tung Lee, Yin-Fu Huang, Shih-Chin Lien, Shyi-Yuan WU
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Publication number: 20120012900Abstract: A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.Type: ApplicationFiled: July 14, 2010Publication date: January 19, 2012Inventors: Ming-Tung LEE, Shih-Chin LIEN, Chia-Huan CHANG