Patents by Inventor Ming Wei

Ming Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240155799
    Abstract: An assembly for securing an electrical component to a server is disclosed. The assembly includes a structural case configured to receive and secure in place an electrical component for the server; a pair of rail holders mounted to the structural case, each rail holder of the pair of rail holders having a plurality of mounting holes that includes a first hole and a second hole; and a pair of latches, each latch of the pair of latches being movably mounted to a respective one of the pair of rail holders, each latch having a finger end that is coupled to a hook end via a bridge portion. The finger end and the hook end are inserted, respectively, into the first hole and the second hole of the respective one of the pair of rail holder, and independently and flexibly move relative to the bridge portion in response to applied pressure.
    Type: Application
    Filed: December 16, 2022
    Publication date: May 9, 2024
    Inventors: Yaw-Tzorng TSORNG, Hung-Wei CHEN, Ming-Lung WANG
  • Publication number: 20240153896
    Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240153440
    Abstract: An interleaving driving method of light emitting diode array comprises: receiving image signal; converting the image signal into gray scale signals, the gray scale signals correspond to the plurality of light emitting channels, respectively, to execute multiple steps. The multiple steps include: generating a high gray scale data group and a low gray scale data group; when there is data in the high gray scale data group, drive the light emitting diode channel corresponding to the target gray scale signal during a first turn on time interval; when there is data in the low gray scale data group, drive the light emitting diode channel corresponding to the target gray scale signal during a second turn on time interval which does not overlap the first turn on time interval and a first gray scale signal and a second gray scale signal of the gray scale signals does not overlap each other.
    Type: Application
    Filed: March 9, 2023
    Publication date: May 9, 2024
    Applicant: MACROBLOCK,INC.
    Inventors: Kai En LIN, Che Wei CHANG, Ming Jia WU
  • Publication number: 20240153899
    Abstract: A method includes polishing a semiconductor substrate of a first die to reveal first through-vias that extend into the semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a plurality of bond pads in the dielectric layer. The plurality of bond pads include active bond pads and dummy bond pads. The active bond pads are electrically coupled to the first through-vias. The first die is bonded to a second die, and both of the active bond pads and the dummy bond pads are bonded to corresponding bond pads in the second die.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Chih-Chia Hu
  • Patent number: 11978801
    Abstract: A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Jou Lian, Chun-Neng Lin, Chieh-Wei Chen, Tzu-Ang Chiang, Ming-Hsi Yeh
  • Patent number: 11978716
    Abstract: A 3DIC structure includes a die, a conductive terminal, and a dielectric structure. The die is bonded to a carrier through a bonding film. The conductive terminal is disposed over and electrically connected to the die. The dielectric structure comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed laterally aside the die. The second dielectric layer is disposed between the first dielectric layer and the bonding film, and between the die and the boding film. A second edge of the second dielectric layer is more flat than a first edge of the first dielectric layer.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Feng Yeh, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 11977423
    Abstract: Methods and systems for thermal management of hardware resources that may be used to provide computer implemented services are disclosed. The disclosed thermal management method and systems may improve the likelihood of data processing systems providing desired computer implemented services by improving the thermal management of the hardware resources without impairment of storage devices. To improve the likelihood of the computer implemented services being provided, the systems may proactively identify whether storage devices subject to impairment due to dynamic motion are present. If such storage devices are present, then the system may automatically take action to reduce the likelihood of the storage devices being subject to dynamic motion sufficient to impair their operation.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: May 7, 2024
    Assignee: Dell Products L.P.
    Inventors: Hung-Pin Chien, Jyh-Yinn Lin, Yu-Wei Chi Liao, Chien Yen Hsu, Ming-Hui Pan
  • Publication number: 20240138364
    Abstract: Disclosed is an air microorganism enrichment device in farms, and relates to the technical field of air microorganism collection.
    Type: Application
    Filed: January 11, 2023
    Publication date: May 2, 2024
    Inventors: Shaolun ZHAI, Chunling LI, Yan LI, Xia ZHOU, Ming LIAO, Mingfei SUN, Jianfeng ZHANG, Huahua KANG, Wenkang WEI, Ting YU
  • Publication number: 20240141547
    Abstract: The present invention relates to a preparation method of a P-type high-resistance and ultra-high-resistance Czochralski monocrystalline silicon substrate. According to the present invention, an oxygen concentration in a silicon wafer is controlled to match with a resistivity, so as to realize that a conductive type of the silicon substrate does not change after a device is manufactured, and that the silicon substrate has a high resistivity. The oxygen concentration and the resistivity in silicon crystal can be adjusted separately or together; and operation is flexible, and a yield of a high-resistance silicon crystal is greatly improved.
    Type: Application
    Filed: March 2, 2023
    Publication date: May 2, 2024
    Applicant: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY CHINESE ACADEMY OF SCIENCES
    Inventors: Xing Wei, Ming Hao Li, Rong Wang Dai, Zi Wen Wang, Zhong Ying Xue
  • Publication number: 20240145421
    Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 2, 2024
    Inventors: Kuan-Neng CHEN, Zhong-Jie HONG, Chih-I CHO, Ming-Wei WENG, Chih-Han CHEN, Chiao-Yen WANG, Ying-Chan HUNG, Hong-Yi WU, CHENG-YEN HSIEH
  • Publication number: 20240145632
    Abstract: A micro light emitting device includes an epitaxial structure, a conductive layer, and a first insulating layer. The epitaxial structure has a first surface and a second surface opposite to the first surface, and includes a first semiconductor layer, an active layer and a second semiconductor layer that are arranged in such order in a direction from the first surface to the second surface. The conductive layer is formed on a surface of the first semiconductor layer away from the active layer. The first insulating layer is formed on the surface of the first semiconductor layer away from the active layer, and exposes at least a part of the conductive layer.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 2, 2024
    Inventors: Ming-Chun TSENG, Shaohua HUANG, Hongwei WANG, Kang-Wei PENG, Su-Hui LIN, Xiaomeng LI, Chi-Ming TSAI, Chung-Ying CHANG
  • Publication number: 20240147286
    Abstract: Apparatus and methods are provided for UE-assisted tethering report. In one novel aspect, UE-assisted tethering report is generated with UE-assisted procedure based on latency measurement configuration. In one embodiment, the UE-assisted tethering report includes one or more elements comprising one bit to inform the activation of tethering mode, latency of packet transmission, and other side-information related to tethering path. In one embodiment, the UE-assisted procedure is inserting a measurement timestamp or recording timing of a predefined transport block (TB) of the packet. In another novel aspect, the UE performs a jitter measurement for an extended reality (XR) traffic, sends a UE-assisted information report for an end-to-end path of the XR traffic based on the jitter measurements, wherein the UE-assisted information includes one or more elements comprising jitter information and burst arrival time.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 2, 2024
    Inventors: JING-WEI CHEN, Tao Chen, Yih-Shen Chen, Ming-Yuan Cheng
  • Publication number: 20240146091
    Abstract: A vehicle power management system and a power management method thereof are provided. The power management method includes: determining, by a microcontroller, whether or not a voltage of an ignition-off signal is less than a voltage threshold when the microcontroller receives the ignition-off signal; stopping a vehicle power supply from charging a backup battery, and using the vehicle power supply to charge a back-end load; activating a counter of the microcontroller; stopping the vehicle power supply from charging the back-end load, and using the backup battery to charge the back-end load when a counting time of the counter reaches a first time threshold; sending, by the microcontroller, the ignition-off signal to the back-end load when the counting time of the counter reaches a second time threshold; and stopping the backup battery from charging the back-end load when the counting time of the counter reaches a third time threshold.
    Type: Application
    Filed: April 17, 2023
    Publication date: May 2, 2024
    Inventors: MING-ZONG WU, CHUN-KAI CHANG, LI-WEI CHENG
  • Patent number: 11974479
    Abstract: An electrical connection structure is provided. The electrical connection structure includes a through hole, a first pad, a second pad and a conductive bridge. The through hole has a first end and a second end. The first pad at least partially surrounds the first end of the through hole and is electrically connected to a first circuit. The second pad is located at the second end of the through hole and is electrically connected to a second circuit. The conductive bridge is connected to the first pad and second pad through the through hole, thereby making the first and second circuits electrically connected to each other.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: April 30, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Shun-Yuan Hu, Chin-Lung Ting, Li-Wei Mao, Ming-Chun Tseng, Kung-Chen Kuo, Yi-Hua Hsu, Ker-Yih Kao
  • Patent number: 11969448
    Abstract: A probiotic composition for improving an effect of a chemotherapeutic drug of Gemcitabine on inhibiting pancreatic cancer is disclosed in the present disclosure. The probiotic composition comprises an effective amount of Lactobacillus paracasei GMNL-133, an effective amount of Lactobacillus reuteri GMNL-89, and a pharmaceutically acceptable carrier, wherein the Lactobacillus paracasei GMNL-133 was deposited in the China Center for Type Culture Collection on Sep. 26, 2011 under an accession number CCTCC NO. M 2011331, and the Lactobacillus reuteri GMNL-89 was deposited in the China Center for Type Culture Collection on Nov. 19, 2007 under an accession number CCTCC NO. M 207154. A method for improving the effect of the chemotherapeutic drug of Gemcitabine on inhibiting pancreatic cancer is further disclosed in the present disclosure.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 30, 2024
    Assignee: GENMONT BIOTECH INC.
    Inventors: Wan-Hua Tsai, I-ling Hsu, Shan-ju Hsu, Wen-ling Yeh, Ming-shiou Jan, Wee-wei Chieng, Li-jin Hsu, Ying-chun Lai
  • Patent number: 11971601
    Abstract: An imaging lens assembly includes a plurality of optical elements and an accommodating assembly, wherein the accommodating assembly is for containing the optical elements. The accommodating assembly includes a conical-shaped light blocking sheet and a lens barrel. The conical-shaped light blocking sheet includes an out-side portion and a conical portion, and the conical portion is connected to the out-side portion. The conical portion includes a conical structure tapered from the out-side portion toward one of an object-side and an image-side along the optical axis. The lens barrel is disposed on one side of the conical portion. The optical elements include a most object-side optical element, a most image-side optical element and at least one optical element. The conical structure of the conical-shaped light blocking sheet is physically contacted with only one of the lens barrel, the most object-side optical element and the most image-side optical element.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: April 30, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Yu-Chen Lai, Chih-Wei Cheng, Ming-Ta Chou, Ming-Shun Chang
  • Patent number: 11974191
    Abstract: A method (50) of, a node device (100) and a computer program product arranged for alerting node devices in a network of operatively interconnected node devices by transmitting an alerting message comprising a geographic location address of an originator node device (21) transmitting the alerting message and a moving direction (12) of an object (11) receiving service from the originator node device (21). When a receiving node device (24, 25) determines, based on its geographic location address, the geographic location address of the originator node device (21) and the moving direction (12), that the object (11) is approaching the receiving node device (24, 25), it transmits the alerting message comprising the geographic location address of the originator node device (21) and the moving direction (12).
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: April 30, 2024
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Lei Feng, Chang Jie Wang, Gong Ming Wei
  • Patent number: 11973170
    Abstract: A semiconductor package includes a photonic die, an encapsulated electronic die, a substrate, and a lens structure. The photonic die includes an optical coupler. The encapsulated electronic die is disposed over and bonded to the photonic die. The encapsulated electronic die includes an electronic die and an encapsulating material at least laterally encapsulating the electronic die. The substrate is disposed over and bonded to the encapsulated electronic die. The lens structure is disposed over the photonic die and is overlapped with the optical coupler from a top view. The optical coupler is configured to be optically coupled to an optical signal source through the lens structure.
    Type: Grant
    Filed: October 5, 2022
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Jie Chen
  • Publication number: 20240136226
    Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Li-Wei CHU, Ying-Chi SU, Yu-Kai CHEN, Wei-Yip LOH, Hung-Hsu CHEN, Chih-Wei CHANG, Ming-Hsing TSAI
  • Publication number: 20240130276
    Abstract: A riding mowing device includes a seat used for a user to sit on and including a seat cushion and a backrest; a frame for supporting the seat; a cutting assembly including a cutting deck and a mowing element for mowing grass, where the mowing element is at least partially accommodated in the cutting deck, and the cutting assembly is mounted to the frame; a traveling assembly for driving the riding mowing device to travel; a control circuit board for controlling at least the cutting assembly and the traveling assembly; and a power supply assembly for supplying power to at least the cutting assembly and the traveling assembly. At least part of the control circuit board is disposed between the seat and the power supply assembly.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 25, 2024
    Inventors: Li Li, Tianfang Wei, Fan Gao, Liang Chen, Haishen XU, Ming Gao, Min Zhang, Tao Zhang, Jiajun Huang, Yunfei Gao