Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.

Abstract: A display panel includes a substrate, a first isolation structure, a second isolation structure and a plurality of light emitting structures. The first isolation structure is disposed on the substrate and includes a plurality of through holes. The second isolation substrate is laminated on the first isolation substrate and fills up the plurality of through holes of the first isolation substrate. The plurality of light emitting structures are disposed on the substrate and are isolated from each other via the second isolation structure.

Abstract: Provided is a display panel, including a substrate, multiple pixel circuits, an insulating layer, multiple first electrodes, a first isolation structure, and a second isolation structure. The pixel circuits are located on the substrate. The insulating layer is located on the pixel circuits and has multiple through holes. The first electrodes are located on the insulating layer and are respectively electrically connected to the pixel circuits through the through holes. The first isolation structure is located on the insulating layer and overlaps the through holes. The second isolation structure includes multiple separating parts and multiple cover parts. The separating parts and the first isolation structure at least partially overlap, and the cover parts respectively overlap the through holes and the first isolation structure.

Abstract: An organic light-emitting panel, including a substrate, a planarization layer, a reflective layer and a bank layer, is provided. The substrate has a display region and a periphery region beside the display region. The planarization layer is disposed on the substrate and has an indentation. The reflective layer is disposed on the planarization layer. The reflective layer is formed along a sidewall of the indentation. The bank layer is disposed on the planarization layer, covers the indentation, and has a periphery taper surface. The indentation is adjacent to the periphery taper surface and is closer to the display region than the periphery taper surface. A fabrication method of the above organic light-emitting panel is also provided.

Abstract: A display panel includes a substrate, a first isolation structure, a second isolation structure and a plurality of light emitting structures. The first isolation structure is disposed on the substrate and includes a plurality of through holes. The second isolation substrate is laminated on the first isolation substrate and fills up the plurality of through holes of the first isolation substrate. The plurality of light emitting structures are disposed on the substrate and are isolated from each other via the second isolation structure.

Abstract: An organic light-emitting panel, including a substrate, a planarization layer, a reflective layer and a bank layer, is provided. The substrate has a display region and a periphery region beside the display region. The planarization layer is disposed on the substrate and has an indentation. The reflective layer is disposed on the planarization layer. The reflective layer is formed along a sidewall of the indentation. The bank layer is disposed on the planarization layer, covers the indentation, and has a periphery taper surface. The indentation is adjacent to the periphery taper surface and is closer to the display region than the periphery taper surface. A fabrication method of the above organic light-emitting panel is also provided.

Abstract: A method for manufacturing a semiconductor package includes: (a) providing a package device, the package device comprising a substrate, a package body and a plurality of connecting elements, the substrate having a first surface, the package body being disposed adjacent to the first surface of the substrate, and the connecting elements being disposed adjacent to the first surface of the substrate and encapsulated by the package body; and (b) removing a portion of the package body along one or more machining paths to expose the connecting elements, wherein each machining path has one or more first paths passing over, between, or along a side of at least two connecting elements, wherein a portion of each of the at least two connecting elements is within the package body, and another portion of each of the at least two connecting elements protrudes from a surface of the package body.

Abstract: The present disclosure relates to a semiconductor package and a method for manufacturing the same. The semiconductor package includes a substrate, a package body and at least two connecting elements. The substrate has a first surface. The package body is disposed adjacent to the first surface of the substrate, and the package body defines a groove having a substantially flat bottom surface. The connecting elements are disposed adjacent to the first surface of the substrate. A portion of each of the connecting elements is within the package body, and another portion of each of the connecting elements protrudes from the substantially flat bottom surface of the groove.

Abstract: A thin film transistor array substrate includes a substrate, a plurality of poly-silicon islands and a plurality of gates. The substrate has a display region, a gate driver region and a source driver region. Each poly-silicon island disposed on the substrate has a source region, a drain region and a channel region disposed therebetween. The poly-silicon islands include several first poly-silicon islands and several second poly-silicon islands. The first poly-silicon islands having main grain boundaries and sub grain boundaries are only disposed within the display region and the gate driver region. The main grain boundaries of the first poly-silicon islands are only disposed within the source regions and/or the drain regions. The second poly-silicon islands are disposed in the source driver region. Grain sizes of the first poly-silicon islands are substantially different from those of the second poly-silicon islands. Gates corresponding to the channel regions are disposed on the substrate.

Abstract: A thin film transistor array substrate includes a substrate, a plurality of poly-silicon islands and a plurality of gates. The substrate has a display region, a gate driver region and a source driver region. Each poly-silicon island disposed on the substrate has a source region, a drain region and a channel region disposed therebetween. The poly-silicon islands include several first poly-silicon islands and several second poly-silicon islands. The first poly-silicon islands having main grain boundaries and sub grain boundaries are only disposed within the display region and the gate driver region. The main grain boundaries of the first poly-silicon islands are only disposed within the source regions and/or the drain regions. The second poly-silicon islands are disposed in the source driver region. Grain sizes of the first poly-silicon islands are substantially different from those of the second poly-silicon islands. Gates corresponding to the channel regions are disposed on the substrate.

Abstract: A thin film transistor array substrate includes a substrate, a plurality of poly-silicon islands and a plurality of gates. The substrate has a display region, a gate driver region and a source driver region. Each poly-silicon island disposed on the substrate has a source region, a drain region and a channel region disposed therebetween. The poly-silicon islands include several first poly-silicon islands and several second poly-silicon islands. The first poly-silicon islands having main grain boundaries and sub grain boundaries are only disposed within the display region and the gate driver region. The main grain boundaries of the first poly-silicon islands are only disposed within the source regions and/or the drain regions. The second poly-silicon islands are disposed in the source driver region. Grain sizes of the first poly-silicon islands are substantially different from those of the second poly-silicon islands. Gates corresponding to the channel regions are disposed on the substrate.

Abstract: A TFT including a gate, a gate insulation layer, an oxide semiconductor layer, a translucent layer, a source, and a drain. The gate insulation layer covers the gate. The oxide semiconductor layer is disposed on the gate insulation layer and located above the gate. The oxide semiconductor layer includes an oxide channel layer and two ohmic contact layers. The ohmic contact layers are respectively located beside the oxide channel layer and connected with the oxide channel layer. The translucent layer is located above the oxide channel layer. The source and the drain are disposed on the gate insulation layer and the ohmic contact layers. The source and the drain are electrically insulated from each other.

Abstract: A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.

Abstract: A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.

Abstract: A TFT including a gate, a gate insulation layer, an oxide semiconductor layer, a translucent layer, a source, and a drain. The gate insulation layer covers the gate. The oxide semiconductor layer is disposed on the gate insulation layer and located above the gate. The oxide semiconductor layer includes an oxide channel layer and two ohmic contact layers. The ohmic contact layers are respectively located beside the oxide channel layer and connected with the oxide channel layer. The translucent layer is located above the oxide channel layer. The source and the drain are disposed on the gate insulation layer and the ohmic contact layers. The source and the drain are electrically insulated from each other.

Abstract: A low temperature polysilicon thin film transistor and method of manufacturing the same is provided. The low temperature polysilicon thin film transistor comprises a channel region. Among others, one feature of the method according to the present invention is the performance of a plasma treatment to adjust the threshold voltage of the low temperature polysilicon thin film transistor. Because the threshold voltage of the low temperature polysilicon thin film transistor can be adjusted through a plasma treatment, the manufacturing process is more flexible.

Abstract: A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.

Abstract: A method of fabricating a thin film transistor including: forming a gate on a substrate; forming a gate insulation layer on the substrate to cover the gate; forming an oxide semiconductor layer on the gate insulation layer; forming a translucent layer on a partial region of the oxide semiconductor layer; performing an optical annealing process to transform the oxide semiconductor layer into an oxide channel layer and two ohmic contact layers by using the translucent layer as a mask, where the oxide channel layer is located under the translucent layer, and the ohmic contact layers are respectively located beside the oxide channel layer and are connected with the oxide channel layer; and forming a source and a drain electrically insulated from each other on the gate insulation layer and the ohmic contact layers.

Abstract: A TFT substrate includes a substrate and at least a TFT disposed thereon. The TFT includes a semiconductor island and at least a gate. The semiconductor island has a source region, a drain region, and a channel region interposed therebetween. The semiconductor island has sub-grain boundaries. The gate corresponds to the channel region. A first included angle between an extending direction of the gate and a line connecting the centroid of the source region with the centroid of the drain region is not substantially equal to 90 degrees. A second included angle between the sub-grain boundaries in the channel region and the line connecting the centroid of the source region with the centroid of the drain region is not substantially equal to 0 degree or 90 degrees. Additionally, a method of fabricating a TFT substrate, an electronic apparatus, and a method of fabricating the electronic apparatus are also provided.

Abstract: A substrate board and a manufacturing method of a package structure are provided. The substrate board includes a first surface, a die-attaching area, a cutting area, a plurality of first pads and a first solder mask. The die-attaching area for attaching a die is located on the first surface. The first pads are disposed on the first surface. The first solder mask is partially disposed on the first surface to expose part of the cutting area and the first pads. The first solder mask is divided into a first inner area and a first outer area via the cutting area. The die-attaching area and the first pads are located in the first inner area. Wherein, part of the first mask is located on the cutting area for connecting the first inner area and the first outer area.