Abstract: A display apparatus includes a wireless transmission unit and a display panel. The display panel includes a substrate, a plurality of pixel units and a signal line. The substrate includes a display region and a periphery region. The periphery region surrounds the display region. The pixel units are disposed on the display region. Each of the pixel units includes an active device and a pixel electrode. The active device is electrically connected to the pixel electrode. The signal line is on the periphery region. As viewed from a top view, the signal line has an annular shape having a gap and surrounds the display region.

Abstract: Provided are a semiconductor device and method of forming the same. The semiconductor device includes active components and a first barrier pattern. The active components are on a substrate. Each of the active components includes base insulation patterns on the substrate, gate electrodes on the substrate and spaced apart from each other with the base insulation patterns interposed therebetween, a gate dielectric layer on the gate electrodes and the base insulation patterns, a channel pattern on the gate dielectric layer, source electrodes on the channel pattern and spaced apart from each other, a drain electrode on the channel pattern and between the source electrodes, and second insulation patterns between the source electrodes and the drain electrode. The first barrier pattern disposed on the gate dielectric layer surrounds the channel patterns, the source electrodes, the drain electrodes, and the second insulation patterns of each of the active components.

Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming an interconnect structure over a substrate. The method also includes forming a passivation layer over the interconnect structure. The method further includes forming an opening in the passivation layer to expose a portion of the interconnect structure. In addition, the method includes sequentially forming a lower barrier film, an upper barrier film, and an aluminum-containing layer in the opening. The lower barrier film and the upper barrier film are made of metal nitride, and the upper barrier film has a nitrogen atomic percentage that is higher than a nitrogen atomic percentage of the lower barrier film and has an amorphous structure.

Abstract: A method for switching audio-visual interfaces and a circuit system are provided. The circuit system is disposed in a sink device. A protocol layer circuit of each of audio-visual interfaces in the sink device includes a status and control data channel control module, which is used to respond to the signals sent by the video sources continuously when the sink device is connected with audio-visual sources via the audio-visual interfaces. The multiple video sources can accordingly send FRL (fixed rate link) signals to the sink device in response to responses made by the sink device. The protocol layer circuit includes an FRL audio-visual packet detection module that starts to detect a rate of an FRL and resolve audio-visual packets for obtaining audio-visual data for the audio-visual interface that the sink device switches to.

Abstract: A continuous wood modification by heat process, that comprises: stacking wooden boards on a trolley at intervals; exerting pressure on said wooden boards; transferring said wooden boards to a heating kiln, pre-heated by microwave and hot air circulation, that has a water vapor flow of 2-5 meter3/hour, a temperature range of 60-100° C., and a humidity range of 50%-100%; transferring said wooden boards to a shallow drying kiln, pre-heated by microwave and hot air circulation, that has a drying temperature of 100-120° C.; transferring said wooden boards to a deep drying kiln, pre-heated by microwave and hot air circulation, that has a drying temperature of 120-120° C., an oxygen content range of 1-10%, and a water vapor flow rate of 1-10 m3/hour; transferring said wooden boards to a carbonization kiln, pre-heated by microwave and hot air circulation, that has a temperature range of 120-180° C.

Abstract: A method is disclosed for storing and reusing the PC description of layout cells. A database stores predefined cells and PC descriptions that were previously calculated by a 3D field solver. Regarding a candidate cell from the layout diagram, the database is searched for a substantial match amongst the predefined cells. If there is a match, then the stored PC description of the matching predefined cell is assigned to the candidate cell in the layout diagram, which avoids having to make a discrete calculation for the PC description. If there is no match, then the 3D field solver is applied to the candidate cell in order to calculate the PC description of the candidate cell. To facilitate reusing the newly calculated PC description, the candidate cell and the newly calculated PC description are stored in the database as a new predefined cell and its corresponding PC description.

Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

Abstract: The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.

Abstract: A two-dimensional array of discrete dielectric template structures is formed over a substrate. A first dielectric spacer matrix may be formed in lower portions of the trenches between the discrete dielectric template structures. A second dielectric spacer matrix layer may be formed in upper portions of the trenches. A pair of a source cavity and a drain cavity may be formed within a volume of each of the discrete dielectric template structures. A source electrode and a drain electrode may be formed in each source cavity and each drain cavity, respectively. The gate electrodes may be formed prior to, or after, formation of the two-dimensional array of discrete dielectric template structures to provide a two-dimensional array of field effect transistors that may be connected to, or may contain, memory elements.

Abstract: A control system may include a direct-current (DC) power bus for charging internal energy storage elements in control devices of the control system. For example, the control devices may be motorized window treatments configured to adjust a position of a covering material to control the amount of daylight entering a space. The system may include a bus power supply that may generate a DC voltage on the DC power bus. For example, the DC power bus may extend from the bus power supply around the perimeter of a floor of the building and may be connected to all of the motorized window treatments on the floor (e.g., in a daisy-chain configuration). An over-power protection circuit may be configured to disconnect the bus power supply if a bus current exceeds a threshold for a period of time.

Abstract: Embodiments of systems and methods for fluid or structure surface disinfection using a series of pulsed lasers are disclosed. In an example, a system for fluid or structure surface disinfection includes a laser source, an optical module, and a controller coupled to the optical module. The laser source is configured to generate a laser stream. The optical module is configured to shape the laser stream and direct the laser stream toward a portion of a surface of a structure. The controller is coupled to the optical module and configured to control the optical module to direct the laser stream toward the portion of the surface of the structure.

Abstract: A cooling system includes a rotor structure, a first end plate and a second end plate. The rotor structure includes a silicon steel, magnets and a shaft. The first end plate is at a first end of the silicon steel, and the first end plate is recessed with a first-shaped oil groove and a second-shaped oil groove. The second end plate is at a second end of the silicon steel, and the second end plate is recessed with a first-shaped oil groove and a second-shaped oil groove. The first-shaped oil groove of the first end plate is connected to the second-shaped oil groove of the second end plate to form a first cooling path. The second-shaped oil groove of the first end plate is connected to the first-shaped oil groove of the second end plate to form a second cooling path.

Abstract: An optical amplification system that includes a combiner and an active fiber. The combiner is configured to receive and combine an input signal and an excitation signal. The active fiber is configured to receive the input signal and the excitation signal from the combiner and generate an amplified input signal. The active fiber is directly coupled to the combiner.

Abstract: A network quality measurement method and system are provided. In the method, a movement path and a movement speed of a vehicle device are determined according to a size of a space and an endurance time of the vehicle device, and the vehicle device is controlled to move on the movement path at the movement speed. During a movement of the vehicle device, a network quality in the space is measured according to a measurement frequency to generate network quality data. Whether the network quality in the space is changed is determined according to the network quality data. Whether there is an obstacle around the vehicle device is detected. When it is determined that the network quality in the space is changed or the obstacle is detected around the vehicle device, at least one of the movement path, the movement speed, and the measurement frequency is adjusted.

Abstract: A pixel array includes octagon-shaped pixel sensors and a combination of visible light pixel sensors (e.g., red, green, and blue pixel sensors) and near infrared (NIR) pixel sensors. The color information obtained by the visible light pixel sensors and the luminance obtained by the NIR pixel sensors may be combined to increase the low-light performance of the pixel array, and to allow for low-light color images in low-light applications. The octagon-shaped pixel sensors may be interspersed in the pixel array with square-shaped pixel sensors to increase the utilization of space in the pixel array, and to allow for pixel sensors in the pixel array to be sized differently. The capability to accommodate different sizes of visible light pixel sensors and NIR pixel sensors permits the pixel array to be formed and/or configured to satisfy various performance parameters.

Abstract: Systems, methods, and other embodiments associated with computing and generating schedule data structures for items in a display are described. In one embodiment, a method includes accessing a sales data structure corresponding to a store and analyzing sales records for items associated with subcategories to calculate a subcategory profit contribution score for each subcategory. The method may also include selecting a first subcategory from the subcategories as a candidate subcategory of items and analyzing the sales records to calculate an item profit contribution score for each of the items assigned to the candidate subcategory. A first item is selected from the candidate subcategory to be placed on a promotional display space, based upon the item profit contribution score of the first item. A schedule data structure is generated that assigns the first item to the promotional display space.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source/drain region arranged within a substrate. A first select gate is arranged over the substrate, and a first memory gate is arranged over the substrate and separated from the source/drain region by the first select gate. An inter-gate dielectric structure is arranged between the first memory gate and the first select gate. The inter-gate dielectric structure extends under the first memory gate. A height of the inter-gate dielectric structure decreases along a direction extending from the first select gate to the first memory gate.

Abstract: A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.

Abstract: A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.

Abstract: Example methods and devices are disclosed. One example method includes receiving, by a first device, configuration information from a second device, where the configuration information is used by the first device to report information about an association relationship between a zero power-reference signal resource and a non-zero power-reference signal resource. The first device can then report the information about the association relationship based on the configuration information.