Abstract: A lock of the present invention includes a housing, a rotating hook, a driving apparatus, and a lock body. An end of the housing includes a front-end opening. The front-end opening faces a same direction as an extending direction of an X-axis, and deviates from a center of a section parallel to a Y-Z plane of the end of the housing that includes the front-end opening, where the X-axis, a Y-axis, and a Z-axis are orthogonal. The rotating hook is arranged in the housing and is rotatable relative to the housing, and includes a front end and a rear end, where the front end at least partially extends out of the front-end opening, and the rear end extends in an opposite direction to the front end. The driving apparatus is arranged in the housing and is movable to change an opening width of the front end. The lock body is arranged in the housing, and when the lock body is locked, the lock body restricts movement of the driving apparatus.

Abstract: A pixel sensor may include a vertically arranged (or vertically stacked) photodiode region and floating diffusion region. The vertical arrangement permits the photodiode region to occupy a larger area of a pixel sensor of a given size relative to a horizontal arrangement, which increases the area in which the photodiode region can collect photons. This increases performance of the pixel sensor and permits the overall size of the pixel sensor to be reduced. Moreover, the transfer gate may surround at least a portion of the floating diffusion region and the photodiode region, which provides a larger gate switching area relative to a horizontal arrangement. The increased gate switching area may provide greater control over the transfer of the photocurrent and/or may reduce switching delay for the pixel sensor.

Abstract: A device and methods of forming the same are described. The device includes a substrate and a first bipolar junction transistor (BJT) disposed over the substrate. The first BJT includes a first base region, a first emitter region, and a first collector region. The device further includes a second BJT disposed over the substrate adjacent the first BJT, and the second BJT includes a second base region, a second emitter region, and a second collector region. The device further includes an interconnect structure disposed over the first and second BJTs, and the interconnect structure includes a first conductive line electrically connected to the first emitter region and the second base region and a second conductive line electrically connected to the first collector region and the second collector region.

Abstract: A method for determining a reference signal sequence, a terminal device, and a network device, the including receiving, by a terminal device, first indication information sent by a network device, determining, by the terminal device, a target resource based on the first indication information, determining, by the terminal device, a reference signal sequence based on parameters of a first bandwidth and parameters of a second bandwidth, and sending or receiving, by the terminal device, the reference signal sequence on the target resource.

Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

Abstract: A method for manufacturing ultra-thin glass substrates and a method for manufacturing a display panel are provided. The method for manufacturing ultra-thin glass substrates includes: providing a glass base material preset with n substrate areas and a skeleton area surrounding the substrate areas; at least forming an etching protection layer on each substrate area of the glass base material; immersing the glass base material in a reaction chamber having etching medium; after the edge of each substrate area is etched to form the stress dissipation edge and the substrate areas are separated from the glass base material, the substrate areas falling down by gravity and falling into the basket; pulling the basket out of the reaction chamber to get the substrate areas separated from the glass base material; removing the etching protection layer to get independent glass substrates.

Abstract: A semiconductor arrangement includes a photodiode extending to a first depth from a first side in a substrate. An isolation structure laterally surrounds the photodiode and includes a first well that extends into a first side of the substrate. A deep trench isolation extends into a second side of the substrate and at least a portion of the deep trench isolation underlies the first well.

Abstract: A semiconductor arrangement includes a photodiode extending to a first depth from a first side in a substrate. An isolation structure laterally surrounds the photodiode and includes a first well that extends into a first side of the substrate. A deep trench isolation extends into a second side of the substrate and at least a portion of the deep trench isolation underlies the first well.

Abstract: In a color display, a color filter layer includes a dielectric layer with an array of photonic crystals, an electroluminescent material disposed on the color filter layer, and electrodes arranged to electrically energize the electroluminescent material to output white light. Each photonic crystal includes a two-dimensional (2D) array of features. The 2D array of features includes a central cavity within which the features of the 2D array of features are omitted. Each photonic crystal is tuned to a resonant wavelength by a periodicity of the two-dimensional array of features. The array of photonic crystals may include, for example, red, green, and blue photonic crystals arranged to form an array of pixels spanning a display area of the color display, in which each pixel includes at least one red photonic crystal, at least one green photonic crystal, and at least one blue photonic crystal.

Abstract: A pixel sensor includes a transfer fin field effect transistor (finFET) to transfer a photocurrent from a photodiode to a drain region. The transfer finFET includes at least a portion of the photodiode, an extension region associated with the drain region, a plurality of channel fins, and a transfer gate at least partially surrounding the channel fins to control the operation of the transfer finFET. In the transfer finFET, the transfer gate is wrapped around (e.g., at least three sides) of each of the channel fins, which provides a greater surface area over which the transfer gate is enabled to control the transfer of electrons. The greater surface area results in greater control over operation of the finFET, which may reduce switching times of the pixel sensor (which enables faster pixel sensor performance) and may reduce leakage current of the pixel sensor relative to a planar transfer transistor.

Abstract: A pixel sensor may include a deep trench isolation (DTI) structure that extends the full height of a substrate in which a photodiode of the pixel sensor is included. Incident light entering the pixel sensor at a non-orthogonal angle is absorbed or reflected by the DTI structure along the full height of the substrate. In this way, the DTI structure may reduce, minimize, and/or prevent the incident light from traveling through the pixel sensor and into an adjacent pixel sensor along the full height of the substrate. This may increase the spatial resolution of an image sensor in which the DTI structure is included, may increase the overall sensitivity of the image sensor, may reduce and/or prevent color mixing between pixel sensors of the image sensor, and/or may decrease image noise after color correction.

Abstract: In various embodiments methods and devices are provided for the detection and/or quantification of an analyte. In certain embodiments a device is provided comprising an aqueous two-phase system (ATPS) comprising a mixed phase solution that separates into a first phase solution and a second phase where, in use, said first phase solution becomes a leading phase and said second phase solution becomes a lagging phase; a lateral-flow assay (LFA); and a probe and/or a development reagent, where in use, said probe associates with said first phase solution in said leading phase of said ATPS and/or said development reagent associates with said second phase solution in said lagging phase of said ATPS. In certain embodiments a “one-pot” system of purifying and amplifying a nucleic acid is provided utilizing, e.g., an ATPS and isothermal amplification reagents.

Abstract: A parameter analysis method and a parameter analysis system for metal additive manufacturing are provided. The parameter analysis method includes: establishing a powder bed model; simulating a multi-track melting result of the powder bed model according to a plurality of laser parameters to generate a melting model; analyzing the melting model to calculate a plurality of position divergences of a plurality of melting powders of the melting model, and defining a plurality of melting surface powders according to the position divergences; analyzing the melting surface powders to calculate a surface average curvature of the melting model; and determining a laser hatch in the laser parameters allows metal additive manufacturing to meet a quality as needed according to whether the surface average curvature is between a first curvature threshold and a second curvature threshold, the first curvature threshold being smaller than the second curvature threshold.

Abstract: In a color display, a color filter layer includes a dielectric layer with an array of photonic crystals, an electroluminescent material disposed on the color filter layer, and electrodes arranged to electrically energize the electroluminescent material to output white light. Each photonic crystal includes a two-dimensional (2D) array of features. The 2D array of features includes a central cavity within which the features of the 2D array of features are omitted. Each photonic crystal is tuned to a resonant wavelength by a periodicity of the two-dimensional array of features. The array of photonic crystals may include, for example, red, green, and blue photonic crystals arranged to form an array of pixels spanning a display area of the color display, in which each pixel includes at least one red photonic crystal, at least one green photonic crystal, and at least one blue photonic crystal.

Abstract: In some embodiments, the present disclosure relates to a method that includes bonding a first wafer to a second wafer to form a wafer stack and removing a top portion of the second wafer. A first trim blade having a first blade width is aligned over the second wafer. The first trim blade is used to form a trench that separates a central portion of the second wafer from a peripheral portion of the second wafer. The trench is arranged at a first distance from an outer perimeter of the second wafer, and extends from a top surface of the second wafer to a trench depth beneath the top surface of the first wafer. A second trim blade having a second blade width is aligned over the peripheral portion, the second blade width being greater than the first blade width. The peripheral portion is removed using the second trim blade.

Abstract: In a color display, a color filter layer includes a dielectric layer with an array of photonic crystals, an electroluminescent material disposed on the color filter layer, and electrodes arranged to electrically energize the electroluminescent material to output white light. Each photonic crystal includes a two-dimensional (2D) array of features. The 2D array of features includes a central cavity within which the features of the 2D array of features are omitted. Each photonic crystal is tuned to a resonant wavelength by a periodicity of the two-dimensional array of features. The array of photonic crystals may include, for example, red, green, and blue photonic crystals arranged to form an array of pixels spanning a display area of the color display, in which each pixel includes at least one red photonic crystal, at least one green photonic crystal, and at least one blue photonic crystal.

Abstract: A pixel array may include a group of time-of-flight (ToF) sensors. The pixel array may include an image sensor comprising a group of pixel sensors. The image sensor may be arranged among the group of ToF sensors such that the image sensor is adjacent to each ToF sensor in the group of ToF sensors.

Abstract: An integrated circuit device includes a dielectric structure within a metal interconnect over a substrate. The dielectric structure includes a cavity. A first dielectric layer provides a roof for the cavity. A second dielectric layer provides a floor for the cavity. A material distinct from the first dielectric layer and the second dielectric layer provides a side edge for the cavity. In a central area of the cavity, the cavity has a constant height. The height may be selected to provide a low parasitic capacitance between features above and below the cavity. The roof of the cavity may be flat. A gate dielectric may be formed over the roof. The dielectric structure is particularly useful for reducing parasitic capacitances when employing back-end-of-line (BEOL) transistors.

Abstract: Some implementations described herein provide pixel sensor configurations and methods of forming the same. In some implementations, one or more transistors of a pixel sensor are included on a circuitry die (e.g., an application specific integrated circuit (ASIC) die or another type of circuitry die) of an image sensor device. The one or more transistors may include a source follower transistor, a row select transistor, and/or another transistor that is used to control the operation of the pixel sensor. Including the one or more transistors of the pixel sensor (and other pixel sensors of the image sensor device) on the circuitry die reduces the area occupied by transistors in the pixel sensor on the sensor die. This enables the area for photon collection in the pixel sensor to be increased.

Abstract: The invention relates to the field of powder coatings, and specifically discloses a heat-curable powder coating composition and a preparation method thereof. The powder coating composition comprises: i) component A comprising at least one amorphous solid polyester resin compound having a Michael donor reactive group; ii) component B comprising at least one amorphous ethylenically unsaturated solid polyester resin with a Michael acceptor reactive group; iii) component C comprising at least one (semi) crystalline solid reactive diluent; iv) component D comprising at least one epoxy group-containing solid substance; v) component E comprising at least one basic catalyst. The present invention also discloses a preparation method of the above heat-curable powder coating composition. By adopting the invention, ultra-low temperature curing can be realized. The curing temperature is as low as 90-110° C., and the curing time is short.