Abstract: Methods and systems are provided for operating various robotic systems. The methods and systems involve applications of platforms that enable multiple-input teleoperation and a high degree of immersiveness for the user. The robotic systems may include multiple arms for manipulators and retrieving information from the environment and/or the robotic system. The robotic methods may include control modification modules for detecting that an operation of a robotic device based on the control commands fails to comply with one or more operational parameters; identifying the non-compliant control command; and generating a modifier for the secondary device to adjust the non-compliant control command to comply with the set of operational parameters.

Abstract: System and method for dynamic termination control to enable use of an increased number of memory modules on a single channel. In some embodiments, six or eight DIMMs are coupled to a single channel. The dynamic termination scheme can include configurations for input bus termination (IBT) on each of the memory modules for the address bus/command bus and configurations for on-die termination (ODT) one each of the memory modules for the data bus.

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

Abstract: In response to a first memory access transaction having a first base address, data fields and a repair fields are retrieved from a first DRAM channel. The data fields include a first data field. The repair fields include a first repair field storing repair data. The repair data is to replace any data in the first data field. In response to a second memory access transaction having a second base address, repair tag fields are retrieved from a second DRAM channel. The repair tag fields include a repair tag field that indicates the repair data is be replace the data stored in the first data field.

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

Abstract: A rack unit configuration is described that includes a first printed circuit board (PCB) assembly interleaved with a second PCB assembly that is inverted with respect to the first PCB assembly. The configuration of the first PCB assembly and the second PCB assembly allow for increased component and power densities within computing systems, memory systems, etc. The increased density may be achieved while allowing sufficient mechanical clearance to allow easy component replacement and servicing (e.g., and hot pluggability). Power density may also be increased with PCB assemblies including nested and interleaved power modules.

Abstract: A memory appliance system is described and includes a processor coupled to one or more communication channels with a command interface, wherein the processor is configured for communicating commands over the communication channels. A plurality of Smart Memory Cubes (SMCs) is coupled to the processor through the communication channels. Each of the SMCs includes a controller that is programmable, and a plurality of memory devices. The controller is configured to respond to commands from the command interface to access content stored in one or more of the plurality of memory devices and to perform data operations on content accessed from the plurality of memory devices.

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

Abstract: The present invention relates to novel fluorinated macrocyclic compounds and methods of treating a hepatitis C infection in a subject in need of such therapy with said macrocyclic compounds. The present invention further relates to pharmaceutical compositions comprising the compounds of the present invention, or pharmaceutically acceptable salts, esters, or prodrugs thereof, in combination with a pharmaceutically acceptable carrier or excipient.

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

Abstract: The present invention relates to novel fluorinated macrocyclic compounds and methods of treating a hepatitis C infection in a subject in need of such therapy with said macrocyclic compounds. The present invention further relates to pharmaceutical compositions comprising the compounds of the present invention, or pharmaceutically acceptable salts, esters, or prodrugs thereof, in combination with a pharmaceutically acceptable carrier or excipient.

Abstract: A self-regenerating chitosan based filter medium for disinfecting and purifying organic pollutants and other pollutants in a gas or liquid is disclosed herein. Porosity and surface charge of said filter medium is manipulative/tunable by varying one or more of the following parameter(s): concentration of chitosan, crosslinking density, amount of copolymers and additives, freezing temperature, freezing profile, and/or types of crosslinker used. The present filter medium is capable of self-regenerating under exposure to ultra-violet light for sufficient time and removing over 90% of the pollutants from each influent flowing through the filter medium.

Abstract: In an asymmetrically terminated communication system, the power consumed to transmit a particular bit value is adjusted based on whether the bit being output is the second, third, fourth, etc. consecutive bit with the same value after a transition to output the particular bit value. The adjustment of the power consumed to transmit the two or more consecutive bits with the same value may be made by adjusting the driver strength during the second, or subsequent, consecutive bits with the same value. The adjustment of the power consumed is performed on the bit value that consumes the most DC power and the other value is typically not adjusted.

Abstract: In an asymmetrically terminated communication system, the power consumed to transmit a particular bit value is adjusted based on whether the bit being output is the second, third, fourth, etc. consecutive bit with the same value after a transition to output the particular bit value. The adjustment of the power consumed to transmit the two or more consecutive bits with the same value may be made by adjusting the driver strength during the second, or subsequent, consecutive bits with the same value. The adjustment of the power consumed is performed on the bit value that consumes the most DC power and the other value is typically not adjusted.

Abstract: An apparatus for heating a substrate during die bonding is disclosed. The apparatus comprises: a substrate carrier configured to hold the substrate; a heating device configured to heat the substrate; a first actuator for effecting relative motion between the substrate carrier and the heating device such that the substrate is relatively indexed with respect to the heating device; a second actuator for effecting relative motion between the substrate carrier and the heating device such that the heating device contacts the substrate to heat different portions of the substrate. In particular, the second actuator is operative to separate the heating device from the substrate in order for the first actuator to relatively index the substrate across the heating device. A method of heating a substrate during die bonding is also disclosed.

Abstract: The present invention relates to novel fluorinated macrocyclic compounds and methods of treating a hepatitis C infection in a subject in need of such therapy with said macrocyclic compounds. The present invention further relates to pharmaceutical compositions comprising the compounds of the present invention, or pharmaceutically acceptable salts, esters, or prodrugs thereof, in combination with a pharmaceutically acceptable carrier or excipient.

Abstract: A method and an apparatus relates to examining respective collections of coefficients out of a plurality of collections of coefficients according to a global coding order of the plurality of collections of coefficients, the respective collections of coefficients having respective priority levels as well as respective pluralities of coding units and truncation points which correspond to the coding units. In response to determining that an examined collection of coefficients out of the plurality of collections of coefficients has a priority level equal to a global priority level, encoding a first un-encoded coding unit according to a local coding order of the collection of coefficients and reducing the priority level of the collection of coefficients; and after each of the collections of coefficients in the plurality are examined, decreasing the global priority level.

Abstract: There are disclosed three fast rate control methods that can efficiently reduce or remove the computation and memory usage redundancy over conventional PCRD methods. The first method, called successive bit-plane rate allocation (SBRA), assigns the maximum allowable bit-rate for each bit-plane of each code-block by using the currently available rate-distortion information only. The second method is called priority scanning rate allocation (PSRA). This first predicts the order of magnitude of each truncation point's rate-distortion slope and then encodes the truncation points based on the order (priority) information. The third method uses PSRA to obtain a significantly smaller amount of data than PCRD for optimal truncation and is called priority scanning with optimal truncation (PSOT). SBRA provides the highest computational complexity and memory usage reduction, and the lowest coding/transmission delay. The computational complexity reduction can be up to about 90% of the entropy coding process.

Abstract: A die bonding apparatus and a bonding method are provided wherein the apparatus comprises a bond head movable between a supply of semiconductor dice and a die bonding site, a pick-up tool attached to the bond head for holding a die to be bonded at the die bonding site and an optical assembly positioned for viewing an orientation of the die bonding site. The bond head is configured such that an orientation of the die being held by the pick-up tool between the optical assembly and the die bonding site is viewable by the optical assembly, whereby the orientation of the die may be aligned with the orientation of the die bonding site.