Patents by Inventor Ming Yu Huang

Ming Yu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200269422
    Abstract: A system for eliminating interference of randomly stacked workpieces is disclosed. The system includes a three-dimensional sensing module, a pick-up apparatus and a control module. The control module is coupled to the three-dimensional sensing module and the pick-up apparatus. The control module is configured to control the three-dimensional sensing module to capture a three-dimensional image, analyze the three-dimensional image to obtain an image information, select a target workpiece to be picked up according to the image information, arrange an interference elimination path for the target workpiece, and control the pick-up apparatus to eliminate interference of the target workpiece according to the interference elimination path.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 27, 2020
    Inventors: Mei-Yu Huang, Ming-Shiou Liu
  • Publication number: 20200268191
    Abstract: A lid structure, which is used for covering an opening of a container, includes a mainbody, an elastic annular element, and a covering assembly. The mainbody includes a through hole. The elastic annular element is integrally disposed on a peripheral region of the mainbody, wherein the elastic annular element is used for positioning the lid structure on the opening. The covering assembly is disposed on the mainbody and includes a spacer element and a covering element. The spacer element is disposed on and covers the through hole. The spacer element includes a plurality of drain holes and a central connecting portion. The covering element is deformably disposed on the central connecting portion.
    Type: Application
    Filed: February 12, 2020
    Publication date: August 27, 2020
    Inventors: Ming Hua Huang, Lung Hsun Song, Yun Ju Wu, Hung Yu Hsieh, Lin Chun Sun
  • Patent number: 10749077
    Abstract: An optoelectronic device includes a semiconductor stack including a first surface and a second surface opposite to the first surface; a first contact layer on the first surface; and a second contact layer on the second surface. The second contact layer is not overlapped with the first contact layer in a vertical direction. The second contact layer includes a plurality of dots separating to each other and formed of semiconductor material.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: August 18, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chun-Yu Lin, Yung-Fu Chang, Rong-Ren Lee, Kuo-Feng Huang, Cheng-Long Yeh, Yi-Ching Lee, Ming-Siang Huang, Ming-Tzung Liou
  • Publication number: 20200251456
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Application
    Filed: April 23, 2020
    Publication date: August 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Patent number: 10725962
    Abstract: An electronic system and a control method thereof are provided. The electronic system includes a first device, a second device and a control device. The first device includes a first processor and a first control module, and the first control module is electrically connected to the first processor. The second device is detachably disposed on the first device. The second device includes a second processor and a second control module, and the second control module is electrically connected to the second processor. The control device is detachably connected to the second device, and the first device, the second device and the control device are coupled to each other.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: July 28, 2020
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Tzu-Jen Mao, Kuan-Pei Lee, Fu-Yu Cai, Chieh Mii, Ya-Yun Huang, Ming-Chih Huang, Tong-Shen Hsiung, Shang-Chih Liang
  • Publication number: 20200227528
    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 16, 2020
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Ruey-Hsin Liu, Shih-Fen Huang
  • Publication number: 20200227529
    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 16, 2020
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Ruey-Hsin Liu, Shih-Fen Huang
  • Publication number: 20200205166
    Abstract: A method and apparatus are disclosed. In an example, a first user equipment (UE) may be configured with a first number of carriers corresponding to a maximum number of carriers that the first UE is able to use concurrently and/or transmit on concurrently. The first UE may receive a plurality of sidelink transmissions on a plurality of carriers. The first UE may derive a plurality of slots for transmitting Physical Sidelink Feedback Channels (PSFCHs) based upon resources associated with the plurality of sidelink transmissions. Responsive to determining that a number of carriers of a second plurality of carriers associated with derived transmissions of the PSFCHs exceeds the first number of carriers, the first UE may prioritize one or more PSFCHs of the PSFCHs based upon a rule. The plurality of slots for transmitting the PSFCHs may be at least partially overlapped in the time domain.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 25, 2020
    Inventors: Chun-Wei Huang, Li-Chih Tseng, Ming-Che Li, Wei-Yu Chen, Li-Te Pan
  • Publication number: 20200205165
    Abstract: Methods and apparatuses for handling collision between sidelink feedback and sidelink data in a wireless communication system are disclosed herein. In one method, a User Equipment (UE) is (pre-)configured to perform one or more sidelink transmissions on multiple carriers, wherein the UE is able to transmit a first number of carriers among the multiple carriers at the same time. The UE selects a first resource for transmitting a first sidelink transmission in a first slot on a first carrier. The UE derives a second resource for transmitting a PSFCH delivering a feedback in a second slot on a second carrier, wherein the second slot is at least partly overlapping with the first slot in a time domain. The UE determines whether to prioritize either the PSFCH or the first sidelink transmission based on a rule when the number of carriers which the UE identifies to transmit in the overlapped slot exceeds the first number of carriers.
    Type: Application
    Filed: December 11, 2019
    Publication date: June 25, 2020
    Inventors: Chun-Wei Huang, Ming-Che Li, Wei-Yu Chen
  • Patent number: 10680620
    Abstract: A frequency generator, includes a control unit, configured to receive an input signal to generate a divisor signal, a phase signal and a circulation signal; a frequency divider, configured to receive the input signal and perform an integer division to the input signal according to the divisor signal, so as to generate a frequency division signal; a circulating delay circuit, coupled to the frequency divider and configured to perform at least one circulating operation to the frequency division signal, and for each circulating operation, generate at least one phase delay signal; a first multiplexer, coupled to the circulating delay circuit and configured to select one signal from the frequency division signal and the at least one phase delay signal according to the phase signal, so as to generate a multiplexed signal; and a retimer, coupled to the first multiplexer and configured to generate an output signal.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: June 9, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Yen-Yin Huang, Jung-Yu Chang, Ming-Feng Hsu
  • Patent number: 10658482
    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Ruey-Hsin Liu, Shih-Fen Huang
  • Publication number: 20200152662
    Abstract: A pixel array substrate including a substrate, an active device, a planarization layer, a first conductive layer, a first insulation layer and a second conductive layer is provided. The active device is disposed on the substrate. The planarization layer covers the active device and has a first opening. The first conductive layer is disposed on the planarization layer and is electrically connected with a first end of the active device. The first insulation layer is disposed on the first conductive layer. The second conductive layer is disposed on the first insulation layer. The first conductive layer and the second conductive layer cover a side surface of the first opening of the planarization layer.
    Type: Application
    Filed: June 14, 2019
    Publication date: May 14, 2020
    Applicant: Au Optronics Corporation
    Inventors: Ming-Yao Chen, Kuo-Yu Huang, Wen-Ching Sung
  • Publication number: 20200135708
    Abstract: A package structure, a die and method of forming the same are provided. The package structure includes a die, an encapsulant, a RDL structure, and a conductive terminal. The die has a connector. The connector includes a seed layer and a conductive on the seed layer. The seed layer extends beyond a sidewall of the conductive pillar. The encapsulant is aside the die and encapsulates sidewalls of the die. The RDL structure is electrically connected to the die. The conductive terminal is electrically connected to the die through the RDL structure.
    Type: Application
    Filed: January 29, 2019
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Li-Hsien Huang, Ming-Shih Yeh
  • Patent number: 10636775
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Patent number: 10629644
    Abstract: An image sensor includes a semiconductor substrate, a photodiode formed in the semiconductor substrate, a microlens disposed over the photodiode, a first transfer transistor, a second transfer transistor and a capacitor. The first transfer transistor and the second transfer transistor are formed on the semiconductor substrate, and a memory node is formed in the semiconductor substrate between the first transfer transistor and the second transfer transistor, wherein the first transfer transistor is coupled to the photodiode. The capacitor is formed between the first transfer transistor and the second transfer transistor, and the capacitor includes a first electrode coupled to the memory node, a second electrode on the first electrode and extending to an edge of the photodiode, and a dielectric layer between the first and the second electrodes.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: April 21, 2020
    Assignee: Powerchip Technology Corporation
    Inventors: Chih-Ping Chung, Ming-Yu Ho, Wen-Hao Huang, Saysamone Pittikoun
  • Patent number: 10611399
    Abstract: A method of evaluating the health status of belt drive in electric power steering system by detecting the occurrence of sliding teeth in the electric power steering system and the frequency of occurrence and the output of the motor. In this way, the user really knows the belt drive health of the electric power steering system.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: April 7, 2020
    Assignee: HIWIN TECHNOLOGIES CORP.
    Inventors: Eric Wang, Yi-Wei Liao, Chun-Yu Huang, Ming-Si Yan, Hsin-Fu Wang
  • Publication number: 20200105816
    Abstract: An image sensor includes a semiconductor substrate, a photodiode formed in the semiconductor substrate, a microlens disposed over the photodiode, a first transfer transistor, a second transfer transistor and a capacitor. The first transfer transistor and the second transfer transistor are formed on the semiconductor substrate, and a memory node is formed in the semiconductor substrate between the first transfer transistor and the second transfer transistor, wherein the first transfer transistor is coupled to the photodiode. The capacitor is formed between the first transfer transistor and the second transfer transistor, and the capacitor includes a first electrode coupled to the memory node, a second electrode on the first electrode and extending to an edge of the photodiode, and a dielectric layer between the first and the second electrodes.
    Type: Application
    Filed: November 19, 2018
    Publication date: April 2, 2020
    Applicant: Powerchip Technology Corporation
    Inventors: Chih-Ping Chung, Ming-Yu Ho, Wen-Hao Huang, Saysamone Pittikoun
  • Publication number: 20200105857
    Abstract: An active device substrate and a manufacturing method thereof are provided. The active device substrate includes a substrate, first and second scan lines, a data line, first and second active devices and first and second pixel electrodes. The first active device includes a first semiconductor channel layer, a first gate, a first source and a first drain. The first gate is electrically connected to the first scan line. The first pixel electrode is electrically connected to the first drain. The second active device includes a second semiconductor channel layer, a second gate and a second drain. The first semiconductor channel layer is connected to a source region of the second semiconductor channel layer. The first semiconductor channel layer and the second semiconductor channel layer belong to same layer. The second gate is electrically connected to the second scan line. The second pixel electrode is electrically connected to the second drain.
    Type: Application
    Filed: August 19, 2019
    Publication date: April 2, 2020
    Applicant: Au Optronics Corporation
    Inventors: Ming-Yao Chen, Kuo-Yu Huang, Wen-Yi Hsu
  • Patent number: 10604009
    Abstract: A dual-shaft gearbox mechanism includes a hollow shaft motor, first and second gear sets, first and second shafts, a clutch and a unidirectional assembly. When the dual-shaft gearbox mechanism is in a first gear, power is outputted via the first gear set and the unidirectional assembly. When the dual-shaft gearbox mechanism is in a second gear, power is outputted via the clutch and the second gear set.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: March 31, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Cheng-Ping Yang, Ming-Hsien Yang, Chia Tsao, Li-Te Huang, Peng-Yu Chen
  • Publication number: 20200091097
    Abstract: A package structure is provided. The package structure includes a dielectric layer on a die, a RDL structure and a conductive terminal. The RDL structure comprises a redistribution layer in and on the dielectric layer. The redistribution layer comprises a via and a conductive plate. The via is located in and penetrating through the dielectric layer to be connected to the die. The conductive plate is on the via and the dielectric layer, and is connected to the die through the via. The conductive terminal is electrically connected to the die through the RDL structure. The via is ring-shaped.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tuan-Yu Hung, Hung-Jui Kuo, Hsin-Yu Pan, Ming-che Ho, Tzu Yun Huang, Yen-Fu Su