Patents by Inventor Ming-Yu Liu

Ming-Yu Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240144568
    Abstract: Apparatuses, systems, and techniques are presented to generate digital content. In at least one embodiment, one or more neural networks are used to generate video information based at least in part upon voice information and a combination of image features and facial landmarks corresponding to one or more images of a person.
    Type: Application
    Filed: September 6, 2022
    Publication date: May 2, 2024
    Inventors: Siddharth Gururani, Arun Mallya, Ting-Chun Wang, Jose Rafael Valle da Costa, Ming-Yu Liu
  • Publication number: 20240134167
    Abstract: An optical path folding element includes a main body, a light absorption film layer and a matte structure. The main body has optical surface including an incident surface, a reflective surface and an emitting surface. A light enters into the optical folding element through the incident surface. The reflective surface reflects the light so as to change a traveling direction thereof. The light exits the optical folding element through the emitting surface. The light absorbing film layer is configured to reduce reflectance and provided adjacent to at least part of the optical surface, and the light absorbing film layer is in physical contact with the main body. The matte structure is disposed adjacent to at least part of the optical surface. The matte structure provides an undulating profile on a surface of the optical path folding element, and the matte structure is formed in one-piece with the main body.
    Type: Application
    Filed: September 24, 2023
    Publication date: April 25, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Ssu-Hsin LIU, Chen Wei FAN, Chien-Hsun WU, Wen-Yu TSAI, Ming-Ta CHOU
  • Patent number: 11961770
    Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
  • Publication number: 20240120679
    Abstract: A bracket and a terminal equipment are provided. The bracket is provided for a terminal device to be installed thereon and includes a bracket body, two installing elements, and at least one holding element. The two installing elements respectively protrude outward from two sides of the bracket body, and each of the two installing elements includes an engaging portion. The two installing elements are configured to be inserted into the terminal device so the terminal device is installed on the bracket, and each of the engaging portions is configured such that each of the installing elements is engaged with and retained in the terminal device. The holding element protrudes outward from the bracket body and is configured to be inserted into a loading hole of the terminal device.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 11, 2024
    Inventors: Yuan-Yu CHEN, Ming-Hung HUNG, Ying Chih LIU
  • Patent number: 11953877
    Abstract: Manufacturing of a shoe or a portion of a shoe is enhanced by executing various shoe-manufacturing processes in an automated fashion. For example, information describing a shoe part may be determined, such as an identification, an orientation, a color, a surface topography, an alignment, a size, etc. Based on the information describing the shoe part, automated shoe-manufacturing apparatuses may be instructed to apply various shoe-manufacturing processes to the shoe part, such as a pickup and placement of the shoe part with a pickup tool.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: April 9, 2024
    Assignee: NILE, Inc.
    Inventors: Dragan Jurkovic, Patrick Conall Regan, Chih-Chi Chang, Chang-chu Liao, Ming-Feng Jean, Kuo-Hung Lee, Yen-Hsi Liu, Hung-Yu Wu
  • Publication number: 20240114162
    Abstract: Systems and methods herein address reference frame selection in video streaming applications using one or more processing units to decode a frame of an encoded video stream that uses an inter-frame depicting an object and an intra-frame depicting the object, the intra-frame being included in a set of intra-frames based at least in part on at least one attribute of the object as depicted in the intra-frame being different from the at least one attribute of the object as depicted in other intra-frames of the set of intra-frames.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Aurobinda Maharana, Arun Mallya, Ming-Yu Liu, Abhijit Patait
  • Publication number: 20240114180
    Abstract: Systems and methods herein address reference frame selection in video streaming applications using one or more processing units to replace, during receipt of an encoded video stream, a first set of frames stored in a cache with a second set of frames based at least in part on an indication within the encoded video stream that the second set of frames includes a non-blurred frame (NBF).
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Aurobinda Maharana, Vignesh Ungrapalli, Ming-Yu Liu
  • Publication number: 20240114144
    Abstract: Systems and methods herein address reference frame selection in video streaming applications using one or more processing units to identify a frame of a sequence of frames as a blurred frame based at least in part on a first variance of motion (VoM) of the frame being less than or equal to an adaptive threshold that is based in part on a moving average of variance of motion (MAoV) determined using one or more reference frames.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Aurobinda Maharana, Vignesh Ungrapalli, Ming-Yu Liu
  • Publication number: 20240095989
    Abstract: Apparatuses, systems, and techniques to generate a video using two or more images comprising objects to be included in the video. In at least one embodiment, objects are identified in two or more images using one or more neural networks, to generate a video to include the objects in the video.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Inventors: Arun Mohanray Mallya, Ting-Chun Wang, Ming-Yu Liu
  • Patent number: 11934959
    Abstract: Apparatuses, systems, and techniques are presented to synthesize consistent images or video. In at least one embodiment, one or more neural networks are used to generate one or more second images based, at least in part, on one or more point cloud representations of one or more first images.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: March 19, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Arun Mallya, Ting-Chun Wang, Ming-Yu Liu, Karan Sapra
  • Patent number: 11929319
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Patent number: 11923429
    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Ruey-Hsin Liu, Shih-Fen Huang
  • Patent number: 11923392
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Jen-Cheng Liu, Kazuaki Hashimoto, Ming-En Chen, Shyh-Fann Ting, Shuang-Ji Tsai, Wei-Chieh Chiang
  • Publication number: 20240072021
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Publication number: 20240071776
    Abstract: A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The substrate has first and second board surfaces opposite to each other. The vias penetrate through the first board surface and the second board surface, and a part of the vias is disposed in a first die-bonding region on which a chip is to be arranged. The electrodes extend from the first board surface to the second board surface through the vias. The dam is formed on the first board surface to surround the first die-bonding region, and the dam has a height higher than that of the chip. The metal shielding layer covers the dam and a part of the first board surface that do not overlap with the electrodes.
    Type: Application
    Filed: December 2, 2022
    Publication date: February 29, 2024
    Inventors: DEI-CHENG LIU, CHIA-SHUAI CHANG, MING-YEN PAN, JIAN-YU SHIH, JHIH-WEI LAI, SHIH-HAN WU
  • Publication number: 20240054609
    Abstract: Apparatuses, systems, and techniques to generate images. In at least one embodiment, one or more neural networks are used to generate a panoramic image from a segmentation mask.
    Type: Application
    Filed: May 10, 2023
    Publication date: February 15, 2024
    Inventors: Xun Huang, Ming-Yu Liu
  • Publication number: 20240020897
    Abstract: Apparatuses, systems, and techniques are presented to generate image data. In at least one embodiment, one or more neural networks are used to cause a lighting effect to be applied to one or more objects within one or more images based, at least in part, on synthetically generated images of the one or more objects.
    Type: Application
    Filed: July 12, 2022
    Publication date: January 18, 2024
    Inventors: Ting-Chun Wang, Ming-Yu Liu, Koki Nagano, Sameh Khamis, Jan Kautz
  • Publication number: 20230328431
    Abstract: A microphone device includes a first circuit board, a plurality of first microphones and a plurality of second microphones. The first microphones are disposed on the first circuit board and arranged along a first spiral about the reference point. The second microphones are disposed on the first circuit board and arranged along a second spiral about the reference point, wherein the second spiral is non-overlapped with the first spiral. The first microphones and the second microphones are point-symmetrical with respect to the reference point, the first microphones and the second microphones form a plurality of microphone sets, and each of the microphone sets comprises one of the first microphones and one of the second microphones which are point-symmetrical with respect to the reference point.
    Type: Application
    Filed: April 7, 2023
    Publication date: October 12, 2023
    Applicant: AVER INFORMATION INC.
    Inventor: Ming-Yu LIU
  • Patent number: 11775829
    Abstract: A latent code defined in an input space is processed by the mapping neural network to produce an intermediate latent code defined in an intermediate latent space. The intermediate latent code may be used as appearance vector that is processed by the synthesis neural network to generate an image. The appearance vector is a compressed encoding of data, such as video frames including a person's face, audio, and other data. Captured images may be converted into appearance vectors at a local device and transmitted to a remote device using much less bandwidth compared with transmitting the captured images. A synthesis neural network at the remote device reconstructs the images for display.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: October 3, 2023
    Assignee: NVIDIA Corporation
    Inventors: Tero Tapani Karras, Samuli Matias Laine, David Patrick Luebke, Jaakko T. Lehtinen, Miika Samuli Aittala, Timo Oskari Aila, Ming-Yu Liu, Arun Mohanray Mallya, Ting-Chun Wang
  • Publication number: 20230274472
    Abstract: Apparatuses, systems, and techniques are presented to generate one or more images. In at least one embodiment, one or more neural networks are used to generate one or more images of one or more objects based, at least in part, on a model of the one or more objects and texture information.
    Type: Application
    Filed: April 27, 2023
    Publication date: August 31, 2023
    Inventors: Xihui LIU, Ming-Yu LIU, Ting-Chun WANG