Patents by Inventor Ming

Ming has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11063005
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first conductive interconnect wire extending in a first direction over a substrate. A second conductive interconnect wire is arranged over the first conductive interconnect wire. A via rail is configured to electrically couple the first conductive interconnect wire and the second conductive interconnect wire. The first conductive interconnect wire and the second conductive interconnect wire extend as continuous structures past one or more sides of the via rail.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kam-Tou Sio, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng, Ru-Gun Liu, Wen-Hao Chen
  • Patent number: 11060950
    Abstract: A device may receive, from a sensor device, cable distance data identifying cable distances along a fiber cable to vibrations experienced by the fiber cable, and may receive location data identifying locations associated with the vibrations. The device may correlate the cable distance data and the location data to generate correlated location data, and may store the correlated location data in a data structure. The device may receive, from the sensor device, data identifying a cable distance along the fiber cable to an alarm condition associated with the fiber cable, and may determine a location of the alarm condition based on the correlated location data and the data identifying the cable distance along the fiber cable to the alarm condition. The device may perform actions based on the alarm location.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: July 13, 2021
    Assignees: Verizon Patent and Licensing Inc., NEC Laboratories America, Inc.
    Inventors: Tiejun J. Xia, Glenn A Wellbrock, Ting Wang, Ming-Fang Huang
  • Patent number: 11063355
    Abstract: A novel bi-directional vector modulator to be used as an active phase shifter is proposed. The advantages of the active phase shifter include: 1) Compact size—By active current combining technique, short transmission lines are used to perform signal combining rather than using area-consuming Wilkinson combiner or splitter; 2) High phase resolution and flexibility—phase interpolation can be performed by vector addition through m-path vector modulators; 3) High efficiency—no signal switch loss, only switched matching capacitor; 4) Simplified signal interconnection; 5) No passive combiner needed—eliminate large size and losses in the passive combiner); 6) Can have unequal combining and/or splitting by changing the gain of vector modulator, which is difficult to realize with passive combining and/or splitting network; and 7) Can combine different signals.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: July 13, 2021
    Assignee: Tubis Technology INC.
    Inventors: Kenny Kun-Long Wu, James June-Ming Wang
  • Patent number: 11060724
    Abstract: A gas appliance includes a burner, a gas valve, and a control device, wherein the gas valve includes a valve body, a flow regulator, a hot film anemometer, and a stepper motor. The valve body communicates with the burner and a gas source. The flow regulator is driven by the stepper motor to change a gas flow rate supplying to the burner. The hot film anemometer is disposed in the valve body and includes a probe exposed to the outlet passage. The control device executes a control method for the gas valve: sensing the gas flow rate in the outlet passage with the hot film anemometer; comparing the gas flow rate sensed by the hot film anemometer with a predetermined gas flow rate, and controlling the stepper motor to drive the flow regulator based on the comparison result, whereby to stabilize the gas flow rate.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: July 13, 2021
    Assignee: GRAND MATE CO., LTD.
    Inventors: Chung-Chin Huang, Chin-Ying Huang, Hsin-Ming Huang, Hsing-Hsiung Huang, Yen-Jen Yeh
  • Patent number: 11060736
    Abstract: A recirculation grill that includes a cooktop and an intake aperture defining a plurality of slats configured for receiving smoke from the cooktop; an interior plenum configured to create a vacuum force to pull air and smoke from the cooktop into the intake aperture; a diffuser positioned within the plenum and extending downwardly and outwardly; a tunnel configured to receive air flow from the plenum and having at least a filter; a blower housing enclosing a variable speed blower fan configured for pulling air and smoke from the cooktop into the intake aperture and through the plenum and into the tunnel; and a variable fan drive (VFD) for controlling the variable speed blower fan and improving the life of the filter. The intake aperture, the plenum, and the blower are configured to achieve 100% visible smoke capture.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: July 13, 2021
    Assignee: ANH Innovation, LLC
    Inventors: Ming H Pi, Drake Kern, Daniel Pi
  • Patent number: 11061493
    Abstract: A mouse roller module includes a roller assembly, a sensing unit and a control unit. The roller assembly includes a stator and a rotator. When the roller assembly is in a first usage mode, the rotator is rotated relative to the stator in response to an applied force of a user. A rotating speed of the rotator relative to the stator is sensed by the sensing unit. If the rotating speed of the rotator relative to the stator reaches a threshold value when the roller assembly is in the first usage mode, the roller assembly is switched form the first usage mode to a second usage mode under control of the control unit. While the first usage mode is switched to the second usage mode, the roller assembly is switched to an enabled state, so that the stator drives rotation of the rotator.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: July 13, 2021
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Li-Kuei Cheng, Yung-Ming Tsai, Chun-Che Wu
  • Patent number: 11061333
    Abstract: A method of manufacturing a semiconductor device and a semiconductor processing system are provided. The method includes the following steps. A photoresist layer is formed on a substrate in a lithography tool. The photoresist layer is exposed in the lithography tool to form an exposed photoresist layer. The exposed photoresist layer is developed to form a patterned photoresist layer in the lithography tool by using a developer. An ammonia gas by-product of the developer is removed from the lithography tool.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Kai Chen, Chia-Hung Chung, Ko-Bin Kao, Su-Yu Yeh, Li-Jen Wu, Zhi-You Ke, Ming-Hung Lin
  • Patent number: 11063596
    Abstract: A frame decoding circuit implemented in an IC die includes a frame synchronizer, receiving an input clock signal and an input frame signal in serial form, to provide an output clock signal. A phase shift of the output clock signal is adjusted according to a detected code by sampling the input frame signal at a center point for every two bits and the detected code being not a correct type. The input clock signal is divided in frequency with the phase shift for providing the output clock signal. A de-serializer unit receives the input frame signal, the input data, the output clock signal from the frame synchronizer, a delay-locked-loop clock signal to de-serialize the input frame signal and the input data for output.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: July 13, 2021
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Hao Wang, Ting-Chin Cho, Hui-Ting Yang, Yung-Sheng Fang, Chang-Ming Liu, Igor Elkanovich, Amnon Parnass
  • Patent number: 11062969
    Abstract: A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: July 13, 2021
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Cheow Khoon Oh, Ming-Chen Lu, Xiaoming Sui, Bo Chen, Vincent Xue
  • Patent number: 11062941
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
  • Patent number: 11059205
    Abstract: A method for fabricating nanoporous polymer thin film includes steps as follows. A polymer thin film is provided, wherein a polymer solution including a polymer is coated on a substrate to form the polymer thin film. A swelling and annealing process is provided, wherein the polymer thin film is disposed inside a chamber with a vapor of a first solvent, the polymer thin film is swollen and annealed to form a swollen polymer thin film, and the swollen polymer thin film includes the polymer and the first solvent. A freezing process is provided, wherein the swollen polymer thin film is cooled to a temperature less than or equal to a crystallization temperature of the first solvent to crystallize the first solvent. A first solvent removing process is provided, wherein the first solvent is removed with a second solvent, such that a nanoporous polymer thin film is obtained.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: July 13, 2021
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Rong-Ming Ho, Mohan Raj Krishnan, Suhail Kizhakkeveettil Siddique, Yu-Cheng Chien
  • Patent number: 11062978
    Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Ming Shih Yeh
  • Patent number: 11063600
    Abstract: A multi-stage clock generation circuit is disclosed. The circuit includes first and second ring oscillators. The ring oscillators include a corresponding plurality of delay elements coupled in series, with a plurality of shunt circuits in parallel with corresponding inverters. The shunt circuits include respective interpolation nodes, which are resistively coupled to input and output nodes of their corresponding inverters. The interpolation nodes of the first ring oscillator are coupled to delay element input and output nodes of the second ring oscillator. Similarly, the interpolation nodes of the second ring oscillator are coupled to delay element input and output nodes of the first ring oscillator.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: July 13, 2021
    Assignee: Apple Inc.
    Inventors: Wenbo Liu, Wei-Ming Lee, Sanjeev K. Maheshwari
  • Patent number: 11061448
    Abstract: A touchpad module includes a touch member, a bracket, an elastic element and a spacer. The bracket is located under the touch member. The elastic element is arranged between the touch member and the bracket. The spacer is arranged between the elastic element and the touch member. While the touch member is pressed down, the touch member is moved downwardly to compress the spacer and the elastic element is pushed by the at least one spacer. Consequently, the elastic element is subjected to deformation and extended toward the corresponding perforation. The present invention further provides a computing device with the touchpad module.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: July 13, 2021
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Tai-Sou Huang, Chia-Feng Lee, Chang-Tse Lee, Chun-Ming Hsu
  • Patent number: 11062521
    Abstract: A virtuality-reality overlapping method is provided. A point cloud map related to a real scene is constructed. Respective outline border vertexes of a plurality of objects are located by using 3D object detection. According to the outline border vertexes of the objects, the point cloud coordinates of the final candidate outline border vertexes are located according to the screening result of a plurality of projected key frames. Then, the point cloud map is projected to the real scene for overlapping a virtual content with the real scene.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: July 13, 2021
    Assignee: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Jia-Wei Hong, Jing-Tong Fu, Ming-Fang Weng
  • Patent number: 11061665
    Abstract: When a host computer determines that a firmware version to be loaded is higher than a firmware version of each chip to be loaded, the host computer sends a loading flag to the chips to be loaded to enable the chips to be loaded enters a loading mode. The host computer redefines multiple controllable physical connections between each chip to be loaded entering the loading mode and a master controller chip connected thereto so that they act as loading buses. Each chip to be loaded executes a loading process according to a frame period and a frame count to receive the load file completely and then executes the IAP command to program its ROM. When each chip to be loaded finishes the loading process, each chip to be loaded jumps out of the load mode, and the host computer restores the definitions of the plurality of controllable physical connections.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: July 13, 2021
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventor: Ming Yang
  • Patent number: 11063792
    Abstract: The invention provides a method for automatically adjusting the gain of a multi-stage equalizer of a serial data receiver, the serial data receiver provides a gain circuit, the gain circuit comprises a multi-stage equalization circuit, and each stage of equalization circuit is arranged in series; the method comprises: Step S1, setting corresponding serial numbers for each stage of equalization circuit in sequence; Step S2, selecting an equalization circuit corresponding to the serial number from the gain circuit according to a preset rule; Step S3, sequentially adjusting the selected equalization circuits of each stage according to the sequence of the serial numbers to obtain corresponding standard adjustment values; and Step S4, adjusting the equalization circuit greater than or equal to the corresponding serial number according to the standard adjustment value. The method has the benefits that the optimal compensation for the signal is realized.
    Type: Grant
    Filed: December 29, 2019
    Date of Patent: July 13, 2021
    Assignee: AMLOGIC (SHANGHAI) CO., LTD.
    Inventors: Weihua Zou, Ming Shi
  • Patent number: 11061339
    Abstract: An apparatus for containing a substrate and a method of manufacturing the apparatus are provided. The apparatus for containing a substrate includes: a base having a periphery and an upward-facing top horizontal planar surface with a plurality of contact elements, the contact elements being used for engaging the substrate to hold the substrate upon the upward-facing top horizontal planar surface, an upward-facing frame-like support surface extending from the upward-facing top horizontal planar surface and surrounding the contact elements at a position proximate to the periphery of the base; and a cover having a downward-facing frame-like support surface being in large-area contact with the upward-facing frame-like support surface to define a cavity for containing the substrate between the base and the cover. The downward-facing and upward-facing frame-like support surfaces in contact with each other are not at the same level as the upward-facing top horizontal planar surface.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: July 13, 2021
    Assignee: GUDENG PRECISION INDUSTRIAL CO., LTD.
    Inventors: Chia-Ho Chuang, Hsin-Min Hsueh, Ming-Chien Chiu
  • Patent number: 11063135
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: July 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ming Kuo, Po-Jen Chuang, Yu-Ren Wang, Ying-Wei Yen, Fu-Jung Chuang, Ya-Yin Hsiao, Nan-Yuan Huang
  • Patent number: D924881
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: July 13, 2021
    Assignee: BenQ Corporation
    Inventors: Jing-Ren Chen, Yu-Ming Hsu