Patents by Inventor Ming

Ming has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10277467
    Abstract: A method of locating endpoint connectors of a network cable comprises: capturing an incoming packet carrying therein a specific identifier from an echo request instruction; determining whether the incoming packet carries therein the specific identifier; and in response to determining that the incoming packet received carries therein the specific identifier, triggering an indicating device indicative of locations of endpoint connectors of a network cable.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chun-Fei Chang, Ming Da Ho, Ming-Pin Hsueh, Ya Hsuan Tsai
  • Patent number: 10276691
    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10273143
    Abstract: The present disclosure involves forming a method of fabricating a Micro-Electro-Mechanical System (MEMS) device. A plurality of openings is formed in a first side of a first substrate. A dielectric layer is formed over the first side of the substrate. A plurality of segments of the dielectric layer fills the openings. The first side of the first substrate is bonded to a second substrate that contains a cavity. The bonding is performed such that the segments of the dielectric layer are disposed over the cavity. A portion of the first substrate disposed over the cavity is transformed into a plurality of movable components of a MEMS device. The movable components are in physical contact with the dielectric the layer. Thereafter, a portion of the dielectric layer is removed without using liquid chemicals.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Chuan Tseng, Chang-Ming Wu, Shih-Chang Liu, Yuan-Chih Hsieh
  • Patent number: 10272492
    Abstract: Support structures are used in certain additive fabrication processes to permit fabrication of a greater range of object geometries. For additive fabrication processes with materials that are subsequently sintered into a final part, an interface layer is formed between the object and support in order to inhibit bonding between adjacent surfaces of the support structure and the object during sintering. The support structure may be a multi-part support structure to mitigate mold lock or facilitate removal from enclosed spaces.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: April 30, 2019
    Assignee: Desktop Metal, Inc.
    Inventors: Michael Andrew Gibson, Jonah Samuel Myerberg, Ricardo Fulop, Ricardo Chin, Matthew David Verminski, Richard Remo Fontana, Christopher Allan Schuh, Yet-Ming Chiang, Anastasios John Hart
  • Patent number: 10274458
    Abstract: A method for detecting a surface coating performance of a cathode active material comprising: providing an acid solution with a predetermined concentration; putting a coated cathode active material in a container; adding the acid solution into the container until the coated cathode active material is completely soaked to form a solid liquid mixture; sealing the container, heating and stirring the solid liquid mixture, and recording a series of pH values of a liquid phase of the solid liquid mixture at different points in time; and determining the surface coating performance of the coated cathode active material by comparing the recorded pH values with standard pH values. A method for detecting a surface coating performance of a cathode active material by detecting metal ion concentrations in the solid liquid mixture is also provided.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: April 30, 2019
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Li Wang, Xiang-Ming He, Xiao-Ying Pang
  • Patent number: 10274817
    Abstract: A mask includes a transparent substrate, a first pattern, a second pattern, and a sub-resolution auxiliary feature. The first pattern and the second pattern are over the transparent substrate. The first pattern has an area of 0.16 ?m2 to 60000 ?m2. The second pattern has an area of 0.16 ?m2 to 60000 ?m2. The sub-resolution auxiliary feature is over the transparent substrate and connects the first pattern and the second pattern.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Hung Lai, Chih-Chung Huang, Chih-Chiang Tu, Chung-Hung Lin, Chi-Ming Tsai, Ming-Ho Tsai
  • Patent number: 10276215
    Abstract: A data storage device fastener seal system can have at least a base, a cover, and a fastener seal. The base may have at least one fastener aperture and a first contact surface while the cover can have a second contact and a fastener hole. The second contact surface may physically contact the first contact surface to enclose a data storage region. The fastener seal can be positioned between the base and cover proximal the fastener aperture with the fastener seal extending less than an inch from the fastener aperture in every direction along a plane parallel to the first and second contact surfaces.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: April 30, 2019
    Assignee: Seagate Technology LLC
    Inventors: Ying Su, Pow Ming Yap, Kok Liang Cho, Chee Xian Lee
  • Patent number: 10275409
    Abstract: A metadata management system receives metadata changes and automatically updates a metadata architecture which maps the data. The metadata changes may be received through a simple user interface by a user or administrator. Once received, the system may automatically update schemas and data transformation code to process data according to the new data mapping preference. The system may handle metadata updates in a multi-tenant system having one or more applications per tenant, and may update data for a single tenant and 1 or more tenant applications in a multitenancy.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: April 30, 2019
    Assignee: DELL PRODUCTS L.P.
    Inventors: David Tung, Hon Yuk Chan, Ketan Bengali, Sasmita Patra, Ming Chang
  • Patent number: 10275593
    Abstract: A computing device includes central processing resources, memory, a network interface, and a security control module. The security control module determines when to change operation of a program of the computing device. When the operation of the program is to be changed, the security control module identifies a first processing resource of the central processing resources that is currently assigned to execute the program and selects a second processing resource of the central processing resources for subsequent execution the program. The security control module then ascertains first execution settings of the program as used by the first processing resource and facilitates conversion of the first execution settings into second execution settings for the second processing resource. The security control module then de-assigns the first processing resource from executing the program and assigns the second processing resource to execute the program.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: April 30, 2019
    Assignee: UNIQUESOFT, LLC
    Inventors: Terrence Ming Swee Heng, Walter Lee Davis
  • Patent number: 10272402
    Abstract: A stirring container and a stirring apparatus are provided. The stirring container includes a barrel and a plurality of stirring paddles. The barrel is defined with an inner surface, an outer surface, and a center axis. The first opening and a second opening are located at two ends of the center axis; and the paddles are fixed on the inner surface of the barrel and extend from the first opening to the second opening and the extending directions thereof are skewed to the center axis. The stirring apparatus includes the aforesaid stirring container, a supporting structure and a rotation module. The supporting structure connects to the outer surface of the barrel to make the barrel rotatable and covers the second opening. The rotation module connects to the outer surface to rotate the stirring container. Thereby, the stirring container and the stirring apparatus can provide better stirring results.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: April 30, 2019
    Assignee: Jiyonson Co., LTD.
    Inventors: Yun-Long Tun, Shih-Ming Hsu
  • Patent number: 10276541
    Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chung-Shi Liu, Chih-Wei Lin, Hui-Min Huang, Hsuan-Ting Kuo, Ming-Da Cheng
  • Patent number: 10276678
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
  • Patent number: 10276506
    Abstract: A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one conductive pad. The protection layer covers the integrated circuit. The protection layer includes a contact opening, and the conductive pad is exposed by the contact opening of the protection layer. The conductive via is embedded in the contact opening of the protection layer, and the conductive via is electrically connected to the conductive pad through the contact opening. A method of fabricating the above-mentioned semiconductor device and an integrated fan-out package including the above-mentioned semiconductor device are also provided.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 10276652
    Abstract: A schottky diode includes a schottky junction, an ohmic junction, a first isolation structure and a plurality of doped regions. The schottky junction includes a first well in a substrate and a first electrode contacting the first well. The ohmic junction includes a junction region in the first well and a second electrode contacting the junction region. The first isolation structure is disposed in the substrate and separates the schottky junction from the ohmic junction. The doped regions are located in the first well and under the schottky junction, wherein the doped regions separating from each other constitute a top-view profile of concentric circles.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hua Yang, Ke-Feng Lin, Ming-Tsung Lee, Shih-Teng Huang, Chih-Chung Wang, Chiu-Te Lee, Shu-Wen Lin
  • Patent number: 10273544
    Abstract: The disclosure provides materials and methods related to using biomarkers for prediction of duration of response to prostate cancer treatment and for treating prostate cancer.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: April 30, 2019
    Assignee: Dana-Farber Cancer Institute, Inc.
    Inventors: Philip W. Kantoff, Ming Yang, Gwo-Shu Mary Lee, Tong Sun, Wanling Xie
  • Patent number: 10276377
    Abstract: Various patterning methods involved with manufacturing semiconductor devices are disclosed herein. A method for fabricating a semiconductor structure (for example, interconnects) includes forming a patterned photoresist layer over a dielectric layer. An opening (hole) is formed in the patterned photoresist layer. In some embodiments, a surrounding wall of the patterned photoresist layer defines the opening, where the surrounding wall has a generally peanut-shaped cross section. The opening in the patterned photoresist layer can be used to form an opening in the dielectric layer, which can be filled with conductive material. In some embodiments, a chemical layer is formed over the patterned photoresist layer to form a pair of spaced apart holes defined by the chemical layer, and an etching process is performed on the dielectric layer using the chemical layer as an etching mask to form a pair of spaced apart holes through the dielectric layer.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Sung Yen, Yu-Hsun Chen, Chen-Hau Wu, Chun-Kuang Chen, Ta-Ching Yu, Ken-Hsien Hsieh, Ming-Jhih Kuo, Ru-Gun Liu
  • Patent number: 10274342
    Abstract: A rotating sensing device includes a base, a rotating element, at least one magnetic element set, at least one magnetic sensing element set, and a processing unit. The magnetic element set is arranged on the rotating element and includes an axial magnetic element and a radial magnetic element. The magnetic sensing element set is arranged on the base and includes an axial magnetic sensing element and a radial magnetic sensing element. When the rotating element is rotated relatively to the base, a magnetic variation relative to the axial magnetic element and a magnetic variation relative to the radial magnetic element are respectively sensed by the axial magnetic sensing element and the radial magnetic sensing element, so as to generate a sensing signal. The processing unit is adapted to obtain a rotation speed, a loading value, and a deflection value. In addition, a rotating sensing method is also provided.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: April 30, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Chin-Ming Chen, Po-Hsiu Ko, Szu-Chia Lin, Meng-Chiou Liao
  • Patent number: 10276536
    Abstract: Structures and formation methods of a chip package are provided. The method includes forming a protective layer to surround a semiconductor die, and the protective layer has opposing first and second surfaces. The method also includes forming a dielectric layer over the first surface of the protective layer and the semiconductor die. The method further includes forming a conductive feature over the dielectric layer such that the conductive feature is electrically connected to a conductive element of the semiconductor die. In addition, the method includes printing a warpage-control element over the second surface of the protective layer and the semiconductor die such that the semiconductor die is between the warpage-control element and the dielectric layer.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hao-Jan Pei, Chih-Chiang Tsao, Wei-Yu Chen, Hsiu-Jen Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: D847033
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: April 30, 2019
    Assignee: ZHEJIANG RIGHT DIGITAL TECHNOLOGY CO., LTD.
    Inventor: Ming Yan
  • Patent number: D847129
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: April 30, 2019
    Assignee: mophie inc.
    Inventors: Nguyen To, Ming Chiao Chiang, Denny Tsai, Hongguo Zhou