Abstract: A photonic package includes a photonic die and an electronic die disposed over a front side of the photonic die. The photonic die includes an optical coupler and a recess extending from a back side of the photonic die toward the front side of the photonic die, wherein the recess includes a first facet at an end of the optical coupler and a second facet opposite to the first facet and non-parallel to the first facet for reflecting light to or from the optical coupler.

Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.

Abstract: A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die. The tier-2 device die is over the tier-1 device die, and the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die. The method further includes forming a second gap-filling region to encapsulate the tier-2 device die, removing the carrier, and forming a through-dielectric via penetrating through the first gap-filling region. The through-dielectric via is overlapped by, and is electrically connected to, the tier-2 device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are on opposing sides of the tier-1 device die.

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Abstract: A method includes forming a photonic integrated circuit including: a first waveguide; a second waveguide over the first waveguide, wherein the second waveguide is optically coupled to the first waveguide; a first external coupler that is optically coupled to the second waveguide; and a first interconnect structure; attaching an electronic die to a first side of the photonic integrated circuit; direct bonding a first photonic die to a second side of the photonic integrated circuit, wherein the first photonic die is optically coupled to the first waveguide after the direct bonding; and forming a second interconnect structure over the first photonic die and the photonic integrated circuit.

Abstract: A method of forming an optical device as well as the optical device itself are described herein in which an interposer substrate is formed with optical devices in order to connect devices both electrically and optically. As such, both electrical signals and optical signals may be transmitted between a first optical device bonded to the interposer substrate and a second optical device bonded to the interposer substrate.

Abstract: A device includes a photonic layer that includes a waveguide and a grating coupler, wherein the waveguide is optically coupled to the grating coupler; an interconnect structure over the photonic layer; an electronic die bonded to the interconnect structure; and a support over the electronic die, wherein the support includes a metalens, wherein the metalens is optically coupled to the grating coupler.

Abstract: A method of forming an optical device as well as the optical device itself are described herein in which a modulator device is bonded to a photonic integrated circuit. The photonic integrated circuit has a modulator that can be used to modulate optical signals from the photonic integrated circuit and the modulator is formed using lithium niobate.

Abstract: A method includes forming a photonic engine. The formation of the photonic engine includes receiving a photonic die including a plurality of grating couplers, and a plurality of micro lenses attached to the photonic die. The plurality of grating couplers and the plurality of micro lenses are configured to be optically inter-coupled in a one-to-one correspondence. A fiber assembly unit is attached to the photonic engine. The fiber assembly unit includes an optical fiber, and a laser merging unit configured to optically inter-couple the plurality of micro lenses and the optical fiber.

Abstract: Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device.

Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. The first semiconductor die has a front side and a backside opposite to each other. The second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. The plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. A total width of the first semiconductor die may be less than a total width of the second semiconductor die.

Abstract: A semiconductor structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The second semiconductor die is bonded to the first bonding structure of the first semiconductor die. The first bonding structure includes a first dielectric layer, a second dielectric layer covering the first dielectric layer, and first conductors embedded in the first dielectric layer and the second dielectric layer, wherein each of the first conductors includes a first conductive barrier layer covering the first dielectric layer and a first conductive pillar disposed on the first conductive barrier layer, and the first conductive pillars are in contact with the second dielectric layer.

Abstract: Seamless bonding layers in semiconductor packages and methods of forming the same are disclosed. In an embodiment, a method includes forming a second passivation layer over a first metal pad and a second metal pad, the first metal pad and the second metal pad being disposed over a first passivation layer of a first semiconductor die; depositing a first bonding material over the second passivation layer to form a first portion of a first bonding layer, wherein at least a portion of a seam in the first bonding layer is between the first metal pad and the second metal pad; thinning the first portion of the first bonding layer to create a first opening from the seam; and re-depositing the first bonding material to fill the first opening and to form a second portion of the first bonding layer.

Abstract: A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

Abstract: A semiconductor device includes a metallic pattern provided above a substrate and extending in a first direction with a first width, a first active metallic feature directly connected to the metallic pattern and extending in a second direction from the metallic pattern with a second width that is smaller than the first width, and a first dummy metallic feature arranged adjacently to the first active metallic feature. The first dummy metallic feature is directly connected to the metallic pattern and extends in the second direction from the metallic pattern while not electrically connected to lines other than the metallic pattern.

Abstract: Optical devices and methods of manufacture are presented in a first optical package is received, the first optical package including a first positioning opening and a receptacle opening. A receptacle is inserted into the receptacle opening and the first positioning opening in order to access an edge coupler within the first optical package.

Abstract: A method of manufacturing an optical device that can include forming a plurality of first metal structures on a first region of a base surface of a die and a second metal structure on a second region of the base surface of the die, wherein the second metal structure has a different shape compared to the at least the first metal structure, and the second metal structure has a bar-type shape. The method can further include bonding the die to a supporting substrate through the plurality of the first metal structures, and applying an underfill material between the base surface of the die and the supporting substrate. In some embodiments, in a cross-sectional view, the underfill material extends from a top surface of the supporting substrate to a sidewall of the die.

Abstract: Optical devices and methods of manufacture are presented in which a fiber array unit is connected to a first optical package. In embodiments the fiber array unit is passively aligned using a first projection and an opening and then actively aligned after being passively aligned. Once aligned, the fiber array unit is adhered using an adhesive.

Abstract: A semiconductor structure includes a photonic die and a conductive connector. The photonic die includes: an insulating layer having a first side and a second side; at least one optical element disposed on the first side of the insulating layer; a through via penetrating through the insulating layer and aside the at least one optical element, and having a metal is in direct contact with the insulating layer; and an interconnect structure disposed over the first side of the insulating layer and electrically connected to the through via. The conductive connector is disposed on the second side of the insulating layer and electrically connected to the through via. A critical dimension of the through via is between a critical dimension of the interconnect structure and a critical dimension of the conductive connector.

Abstract: A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.