Abstract: A method of manufacturing an optical device that can include forming a plurality of first metal structures on a first region of a base surface of a die and a second metal structure on a second region of the base surface of the die, wherein the second metal structure has a different shape compared to the at least the first metal structure, and the second metal structure has a bar-type shape. The method can further include bonding the die to a supporting substrate through the plurality of the first metal structures, and applying an underfill material between the base surface of the die and the supporting substrate. In some embodiments, in a cross-sectional view, the underfill material extends from a top surface of the supporting substrate to a sidewall of the die.

Abstract: A method includes forming a reconstructed wafer, which includes a supporting substrate, an electronic die over the supporting substrate, and a photonic die over the electronic die. The method further includes a first etching process to form a first trench in the reconstructed wafer, and a second etching process to form a second trench. The photonic die has a first sidewall facing the first trench. The second trench extends from a bottom of the first trench to the supporting substrate, and the second etching process results in a second sidewall facing the second trench.

Abstract: In an embodiment, a semiconductor package may include a photonic integrated circuit (PIC) die having a wavelength modulator and a heating element thermally coupled to the wavelength modulator. The semiconductor package may also include an interconnect structure on the PIC die, where the interconnect structure may include a plurality of conductive features and a void. The void overlaps with the heating element and the wavelength modulator from a top view. The package may furthermore include a plurality of conductive connectors over the interconnect structure and electrically connected to the plurality of conductive features.

Abstract: A package structure including at least one die laterally encapsulate by an encapsulant, a bonding film and an interconnect structure is provided. The bonding film is located on a first side of the encapsulant, and the bonding film includes a first alignment mark structure. The package structure further includes a semiconductor material block located on the bonding film. The interconnect structure is located on a second side of the encapsulant opposite to the first side, and the interconnect structure includes a second alignment mark structure. A location of the first alignment mark structure vertically aligns with a location of the second alignment mark structure.

Abstract: Integrated circuit packages and methods of forming the same are provided. In an embodiment, a device includes: a power distribution interposer including: a first bonding layer; a first die connector in the first bonding layer; and a back-side interconnect structure including a power rail connected to the first die connector; and an integrated circuit die including: a second bonding layer directly bonded to the first bonding layer by dielectric-to-dielectric bonds; a second die connector in the second bonding layer, the second die connector directly bonded to the first die connector by metal-to-metal bonds; and a device layer on the second bonding layer, the device layer including a contact and a transistor, the transistor including a first source/drain region, the contact connecting a back-side of the first source/drain region to the second die connector.

Abstract: A semiconductor package including a photonic package coupled to a first side of a package substrate, the photonic package including a semiconductor substrate, an array including multiple rows of coupling lenses on a top surface of the semiconductor substrate, and multiple rows of couplers disposed below the multiple rows of coupling lenses, where each coupler of the multiple rows of couplers is disposed below a corresponding coupling lens of the multiple rows of coupling lenses, first conductive connectors disposed between the photonic package and the first side of the package substrate, where the first conductive connectors are attached to first bond pads on the first side of the package substrate, and where at least one of the first conductive connectors includes a first intermetallic region, and second conductive connectors disposed on a second side of the package substrate that is opposite the first side.

Abstract: A method of forming a semiconductor package includes the following steps. A first die is provided, wherein the first die comprises a plurality of first conductive patterns. A plurality of second conductive patterns are formed over the first die, wherein the second conductive patterns are connected to the first conductive patterns to form a first coil and a second coil surrounding the first coil.

Abstract: A semiconductor package including a thermally conductive bridge and a method of forming are provided. The semiconductor package may include a first semiconductor device having a first substrate and first contact pads on the first substrate, a first thermally conductive feature on the first substrate and extending into the first substrate, a second semiconductor device over the first substrate, wherein the second semiconductor device may include second contact pads electrically connected to the first contact pads, a first thermally conductive bridge over the first semiconductor device and beside the second semiconductor device, and a first encapsulant over the first semiconductor device and along sidewalls of the second semiconductor device and the first thermally conductive bridge.

Abstract: A method includes forming a sacrificial layer on a substrate, and patterning the sacrificial layer to form a first sacrificial block having a first height, and a second sacrificial block having a second height greater than the first height. The second sacrificial block is spaced apart from the first sacrificial block by a space. The method further includes reflowing the first sacrificial block and the second sacrificial block, and performing an etching process to etch the first sacrificial block, the second sacrificial block, and the substrate. As a result of the etching, a first portion of the substrate directly underlying the first sacrificial block forms a micro lens, and a second portion of the substrate directly underlying the second sacrificial block forms a protection wall.

Abstract: A semiconductor device includes a first passivation layer over a circuit and. conductive pad over the first passivation layer, wherein the conductive pad is electrically connected to the circuit. A second passivation layer is disposed over the conductive pad and the first passivation layer, and has a first opening and a second opening. The first opening exposes an upper surface of a layer that extends underneath the conductive pad, and the second opening exposes the conductive pad. A first insulating layer is disposed over the second passivation layer and filling the first and second openings. A through substrate via extends through the insulating layer, second passivation layer, passivation layer, and substrate. A side of the through substrate via and the second passivation layer have a gap that is filled with the first insulating layer. A conductive via extends through the first insulating layer and connecting to the conductive pad.

Abstract: A package includes a first device die, and a second device die bonded to the first device die through hybrid bonding. The second device die is larger than the first device die. A first isolation region encapsulates the first device die therein. The first device die, the second device die, and the first isolation region form parts of a first package. A third device die is bonded to the first package through hybrid bonding. The third device die is larger than the first package. A second isolation region encapsulates the first package therein. The first package, the third device die, and the second isolation region form parts of a second package.

Abstract: Provided is a package structure and a method of forming the same. The method includes bonding a first integrated circuit component onto an interposer, wherein the first integrated circuit component has a recess filled with a sacrificial material therein; forming an underfill layer on the interposer to laterally surround the first integrated circuit component; forming an encapsulant on the interposer to laterally encapsulate the underfill layer and the first integrated circuit component; removing a portion of the encapsulant to expose the sacrificial material within the recess of the first integrated circuit component; and removing the sacrificial material to expose the recess of the first integrated circuit component.

Abstract: A semiconductor device includes a metallic pattern provided above a substrate and extending in a first direction with a first width, a first active metallic feature directly connected to the metallic pattern and extending in a second direction from the metallic pattern with a second width that is smaller than the first width, and a first dummy metallic feature arranged adjacently to the first active metallic feature. The first dummy metallic feature is directly connected to the metallic pattern and extends in the second direction from the metallic pattern while not electrically connected to lines other than the metallic pattern.

Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. The first semiconductor die has a front side and a backside opposite to each other. The second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. The plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. A total width of the first semiconductor die may be less than a total width of the second semiconductor die.

Abstract: A semiconductor package includes a redistribution structure, a first device and a second device attached to the redistribution structure, the first device including: a first die, a support substrate bonded to a first surface of the first die, and a second die bonded to a second surface of the first die opposite the first surface, where a total height of the first die and the second die is less than a first height of the second device, and where a top surface of the substrate is at least as high as a top surface of the second device, and an encapsulant over the redistribution structure and surrounding the first device and the second device.

Abstract: Integrated circuit packages and methods of forming the same are provided. In an embodiment, a device includes: a power distribution interposer including: a first bonding layer; a first die connector in the first bonding layer; and a back-side interconnect structure including a power rail connected to the first die connector; and an integrated circuit die including: a second bonding layer directly bonded to the first bonding layer by dielectric-to-dielectric bonds; a second die connector in the second bonding layer, the second die connector directly bonded to the first die connector by metal-to-metal bonds; and a device layer on the second bonding layer, the device layer including a contact and a transistor, the transistor including a first source/drain region, the contact connecting a back-side of the first source/drain region to the second die connector.

Abstract: A photonic package includes a photonic die and an electronic die disposed over a front side of the photonic die. The photonic die includes an optical coupler and a recess extending from a back side of the photonic die toward the front side of the photonic die, wherein the recess includes a first facet at an end of the optical coupler and a second facet opposite to the first facet and non-parallel to the first facet for reflecting light to or from the optical coupler.

Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.

Abstract: A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die. The tier-2 device die is over the tier-1 device die, and the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die. The method further includes forming a second gap-filling region to encapsulate the tier-2 device die, removing the carrier, and forming a through-dielectric via penetrating through the first gap-filling region. The through-dielectric via is overlapped by, and is electrically connected to, the tier-2 device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are on opposing sides of the tier-1 device die.

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.