Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Abstract: A pharmaceutical composition containing a mixed polymeric micelle and a drug enclosed in the micelle, in which the mixed polymeric micelle, 1 to 1000 nm in size, includes an amphiphilic block copolymer and a lipopolymer. Also disclosed are preparation of the pharmaceutical composition and use thereof for treating cancer.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate and a word line (WL) structure, wherein the substrate includes trenches arranged in parallel intervals; the WL structure is located in the trenches, and includes a dielectric layer and a conductive layer; the dielectric layer covers a bottom surface and a sidewall of the conductive layer; the conductive layer includes a first conductive layer and a second conductive layer; and a first component is doped in the second conductive layer.

Abstract: The present disclosure relates to a memory device with a vertical field effect transistor (VFET) and a method for preparing the memory device. The memory device includes a capacitor contact disposed in a first semiconductor substrate, and a channel structure disposed over a top surface of the first semiconductor substrate. The memory device also includes a first gate structure disposed on a first sidewall of the channel structure, and a second gate structure disposed on a second sidewall of the channel structure. The second sidewall of the channel structure is opposite to the first sidewall of the channel structure. The memory device further includes a bit line contact disposed over the channel structure. The channel structure is electrically connected to a capacitor and a bit line through the capacitor contact and the bit line contact.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including an array area and a peripheral area surrounding the array area; a word line structure positioned in the array area; and a first gate stack positioned on the peripheral area and including: a first gate dielectric layer positioned on the peripheral area; a first gate protection layer positioned on the first gate dielectric layer and including titanium silicon nitride; a first work function layer positioned on the first gate protection layer; and a first gate filler layer positioned on the first work function layer.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; and a first gate stack positioned on the substrate and including: a first gate dielectric layer positioned on the substrate; a first gate protection layer positioned on the first gate dielectric layer and including titanium silicon nitride; a first work function layer positioned on the first gate protection layer; and a first gate filler layer positioned on the first work function layer.

Abstract: An optical semiconductor device with cascade vias is disclosed. The semiconductor device a logic die having a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and having a memory cell area and a memory peripheral area; a first inter-die via positioned in the memory peripheral area; a landing pad positioned on the first inter-die via; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area. The first inter-die via and the first intra-die via are electrically coupled through the landing pad in a cascade manner.

Abstract: The present disclosure relates to a memory device with a vertical field effect transistor (VFET) and a method for preparing the memory device. The memory device includes a capacitor contact disposed in a first semiconductor substrate, and a channel structure disposed over a top surface of the first semiconductor substrate. The memory device also includes a first gate structure disposed on a first sidewall of the channel structure, and a second gate structure disposed on a second sidewall of the channel structure. The second sidewall of the channel structure is opposite to the first sidewall of the channel structure. The memory device further includes a bit line contact disposed over the channel structure. The channel structure is electrically connected to a capacitor and a bit line through the capacitor contact and the bit line contact.

Abstract: The present disclosure provides a semiconductor device structure with conductive contact of different widths and a method for preparing the semiconductor device structure. The semiconductor device structure includes a dielectric layer disposed over a semiconductor substrate, and a first conductive contact penetrating through the dielectric layer. The first conductive contact includes a first metal filling layer and a first metal silicide structure surrounding the first metal filling layer. The semiconductor device structure also includes a second conductive contact penetrating through the dielectric layer. The second conductive contact includes a second metal filling layer and a second metal silicide structure surrounding the second metal filling layer, and a first width of the first conductive contact is different from a second width of the second conductive contact.

Abstract: The present disclosure relates to a memory device with a vertical field effect transistor (VFET) and a method for preparing the memory device. The memory device includes a capacitor contact disposed in a first semiconductor substrate, and a channel structure disposed over a top surface of the first semiconductor substrate. The memory device also includes a first gate structure disposed on a first sidewall of the channel structure, and a second gate structure disposed on a second sidewall of the channel structure. The second sidewall of the channel structure is opposite to the first sidewall of the channel structure. The memory device further includes a bit line contact disposed over the channel structure. The channel structure is electrically connected to a capacitor and a bit line through the capacitor contact and the bit line contact.

Abstract: The present application discloses a semiconductor device with a barrier layer including aluminum fluoride and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a circuit layer positioned on the substrate, a pad layer positioned in the circuit layer and including aluminum and copper, a first barrier layer positioned on the pad layer and including aluminum fluoride, and a first connector positioned on the first barrier layer.

Abstract: The present application discloses a semiconductor device with a barrier layer including aluminum fluoride and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a circuit layer positioned on the substrate, a pad layer positioned in the circuit layer and including aluminum and copper, a first barrier layer positioned on the pad layer and including aluminum fluoride, and a first connector positioned on the first barrier layer.

Abstract: The present application discloses a semiconductor device with a barrier layer including aluminum fluoride and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a circuit layer positioned on the substrate, a pad layer positioned in the circuit layer and including aluminum and copper, a first barrier layer positioned on the pad layer and including aluminum fluoride, and a first connector positioned on the first barrier layer.

Abstract: The present disclosure provides a semiconductor intelligent detection system, an intelligent detection method and a storage medium. The semiconductor intelligent detection system includes: a data import module, configured to acquire a data table to-be-detected; a data storage module, having a process resource database stored therein, a data type of data stored in the process resource database being used to perform data detection on items to-be-detected of a corresponding type; a resource detection module, connected to the data import module and the data storage module; wherein the resource detection module is configured to perform data detection on the items to-be-detected in the data table to-be-detected one by one, and record wrong items to-be-detected in an abnormity information table; and, an abnormity export module, connected to the resource detection module and configured to detect whether the resource detection module has detected the last item to-be-detected in the data table to-be-detected.

Abstract: A sensing device for sensing ion concentration of a solution, including a first substrate, a second substrate, a sensing layer, and two electrodes. The material of the first substrate includes cellulose. The second substrate is located on the first substrate. The sensing layer is located on the second substrate. The two electrodes are separately disposed on the sensing layer to expose the sensing layer and bring a solution in contact with the sensing layer so as to measure the resistance value of the solution and convert the resistance value into the ion concentration of the solution.

Abstract: A reduction-oxidation sensor device and a manufacturing method thereof are provided. The reduction-oxidation sensor device includes a first electrode, at least one sensing structure and a second electrode. The first electrode is located on a substrate. The at least one sensing structure is located on the first electrode and the substrate. The at least one sensing structure includes a metal nanowire layer and a metal oxide layer. The metal nanowire layer is disposed on the first electrode and the substrate. The metal nanowire layer is wrapped by the metal oxide layer. The second electrode is located on the at least one sensing structure.

Abstract: A transparent pressure sensor and a manufacturing method thereof are provided. The transparent pressure sensor includes several layers of transparent electrodes, at least one pressure-sensitive deformation layer between the transparent electrodes, and a metal oxide layer. Each layer of the transparent electrodes is composed of nanowires, and the metal oxide layer is disposed in a space among the nanowires.

Abstract: A pressure sensor and a manufacturing method thereof are provided. The pressure sensor includes a thin-film transistor (TFT) array and a pressure-sensitive layer covering the TFT array. The pressure-sensitive layer includes a plurality of insulating layers and one of one-directional materials arranged on the same plane and two-directional materials. The insulating layers and the one- or two-directional materials are alternately stacked so as to effectively enhance pressure resolution.

Abstract: A gas detecting device configured to be attached to a surface includes a substrate, a semiconductor layer, a light-emitting component, a first electrode and a second electrode. The substrate includes a plurality of stacking layers stacked onto one another, and a material of the substrate includes cellulose nanofibrils (CNF). The substrate is formed by 3-D printing, such that a contact surface of the substrate is tightly attached to the surface. The semiconductor layer is formed on the substrate by 3-D printing. The light-emitting component is disposed on the substrate. The first electrode is coupled to the semiconductor layer and the light-emitting component. The second electrode is coupled to the semiconductor layer and a ground electrode. The first electrode and the second electrode are both disposed on the semiconductor layer and maintain a gap therebetween. A resistance of the semiconductor layer is changed according to a concentration of a designated gas.