Patents by Inventor Mingjiao Liu
Mingjiao Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240072008Abstract: A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.Type: ApplicationFiled: November 7, 2023Publication date: February 29, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jinchang ZHOU, Yusheng LIN, Mingjiao LIU
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Patent number: 11670706Abstract: In a general aspect, method of producing an insulated-gate bipolar transistor (IGBT) device can include forming a termination structure in an inactive region. The inactive region at least partial surround an active region. The method can also include forming a trench extending along a longitudinal axis in the active region. A first mesa can define a first sidewall of the trench, and a second mesa can define a second sidewall of the trench. The first mesa and the second mesa can be parallel with the trench. The method can further include forming, in at least a portion of the first mesa, an active segment of the IGBT device, and, forming, in at least a portion of the second mesa, an inactive segment of the IGBT device.Type: GrantFiled: July 17, 2020Date of Patent: June 6, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Meng-Chia Lee, Ralph N. Wall, Mingjiao Liu, Shamsul Arefin Khan, Gordon M. Grivna
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Patent number: 11233158Abstract: A device includes a first doped semiconductor region and a second oppositely doped semiconductor region that are separated by an undoped or lightly-doped semiconductor drift region. The device further includes a first electrode structure making an ohmic contact with the first doped semiconductor region, and a second electrode structure making a universal contact with the second doped semiconductor region. The universal contact of the second electrode structure allows flow of both electrons and holes into, and out of, the device.Type: GrantFiled: October 29, 2019Date of Patent: January 25, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Mingjiao Liu
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Patent number: 11056581Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT device can also include a first mesa defined by a first sidewall of the trench and in parallel with the trench and a second mesa defined by a second sidewall of the trench and in parallel with the trench. The first mesa can include at least one active segment of the IGBT device and the second mesa can include at least one inactive segment of the IGBT device.Type: GrantFiled: January 31, 2018Date of Patent: July 6, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Mingjiao Liu, Shamsul Arefin Khan, Gordon M. Grivna, Meng-Chia Lee, Ralph N. Wall
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Patent number: 10930524Abstract: In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material is mounted to the device receiving structure. A first electrical interconnect is coupled between the first current carrying terminal of the semiconductor device and a first lead. A second electrical interconnect is coupled between the control terminal of the semiconductor device and a second lead.Type: GrantFiled: May 8, 2019Date of Patent: February 23, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chun-Li Liu, Ali Salih, Mingjiao Liu
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Publication number: 20210050458Abstract: A device includes a first doped semiconductor region and a second oppositely doped semiconductor region that are separated by an undoped or lightly-doped semiconductor drift region. The device further includes a first electrode structure making an ohmic contact with the first doped semiconductor region, and a second electrode structure making a universal contact with the second doped semiconductor region. The universal contact of the second electrode structure allows flow of both electrons and holes into, and out of, the device.Type: ApplicationFiled: October 29, 2019Publication date: February 18, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Mingjiao LIU
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Publication number: 20200350424Abstract: In a general aspect, method of producing an insulated-gate bipolar transistor (IGBT) device can include forming a termination structure in an inactive region. The inactive region at least partial surround an active region. The method can also include forming a trench extending along a longitudinal axis in the active region. A first mesa can define a first sidewall of the trench, and a second mesa can define a second sidewall of the trench. The first mesa and the second mesa can be parallel with the trench. The method can further include forming, in at least a portion of the first mesa, an active segment of the IGBT device, and, forming, in at least a portion of the second mesa, an inactive segment of the IGBT device.Type: ApplicationFiled: July 17, 2020Publication date: November 5, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Meng-Chia LEE, Ralph N. WALL, Mingjiao LIU, Shamsul Arefin KHAN, Gordon M. GRIVNA
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Patent number: 10727326Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT can also include a first mesa defining a first sidewall of the trench and in parallel with the trench and a second mesa defining a second sidewall of the trench and in parallel with the trench. At least a portion of the first mesa can include an active segment of the IGBT device, and at least a portion of the second mesa can include an inactive segment of the IGBT device.Type: GrantFiled: January 31, 2018Date of Patent: July 28, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Meng-Chia Lee, Ralph N. Wall, Mingjiao Liu, Shamsul Arefin Khan, Gordon M. Grivna
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Patent number: 10438932Abstract: A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.Type: GrantFiled: April 16, 2018Date of Patent: October 8, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jinchang Zhou, Yusheng Lin, Mingjiao Liu
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Publication number: 20190267252Abstract: In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material is mounted to the device receiving structure. A first electrical interconnect is coupled between the first current carrying terminal of the semiconductor device and a first lead. A second electrical interconnect is coupled between the control terminal of the semiconductor device and a second lead.Type: ApplicationFiled: May 8, 2019Publication date: August 29, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chun-Li LIU, Ali SALIH, Mingjiao LIU
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Patent number: 10388539Abstract: In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material is mounted to the device receiving structure. The control terminal of the first electrical interconnect is coupled to a first lead by a first electrical interconnect. A second electrical interconnect is coupled between the first current carrying terminal of the semiconductor device and a second lead. The second current carrying terminal of the first semiconductor device is coupled to the device receiving structure or to the interconnect structure.Type: GrantFiled: July 6, 2016Date of Patent: August 20, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chun-Li Liu, Ali Salih, Mingjiao Liu
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Publication number: 20190058056Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT device can also include a first mesa defined by a first sidewall of the trench and in parallel with the trench and a second mesa defined by a second sidewall of the trench and in parallel with the trench. The first mesa can include at least one active segment of the IGBT device and the second mesa can include at least one inactive segment of the IGBT device.Type: ApplicationFiled: January 31, 2018Publication date: February 21, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Mingjiao Liu, Shamsul Arefin Khan, Gordon M. Grivna, Meng-Chia Lee, Ralph N. Wall
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Publication number: 20190058055Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT can also include a first mesa defining a first sidewall of the trench and in parallel with the trench and a second mesa defining a second sidewall of the trench and in parallel with the trench. At least a portion of the first mesa can include an active segment of the IGBT device, and at least a portion of the second mesa can include an inactive segment of the IGBT device.Type: ApplicationFiled: January 31, 2018Publication date: February 21, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Meng-Chia LEE, Ralph N. WALL, Mingjiao LIU, Shamsul Arefin KHAN, Gordon M. GRIVNA
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Patent number: 10177232Abstract: A Schottky device includes a plurality of mesa structures where one or more of the mesa structures includes a doped region having a multi-concentration dopant profile. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type. Trenches having sidewalls and floors are formed in the semiconductor material to form a plurality of mesa structures. A doped region having a multi-concentration impurity profile is formed between two trenches, where the impurity materials of the doped region having the multi-concentration impurity profile are of a second conductivity type. A Schottky contact is formed to at least one of the mesa structures having the doped region with the multi-concentration impurity profile.Type: GrantFiled: July 24, 2017Date of Patent: January 8, 2019Assignee: Semiconductor Components Industries, LLCInventors: Mohammed Tanvir Quddus, Mihir Mudholkar, Mingjiao Liu, Michael Thomason
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Patent number: 10163764Abstract: A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.Type: GrantFiled: August 30, 2017Date of Patent: December 25, 2018Assignee: Semiconductor Components Industries, LLCInventors: Chun-Li Liu, Ali Salih, Balaji Padmanabhan, Mingjiao Liu
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Publication number: 20180240786Abstract: A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.Type: ApplicationFiled: April 16, 2018Publication date: August 23, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jinchang ZHOU, Yusheng LIN, Mingjiao LIU
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Publication number: 20180233491Abstract: A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.Type: ApplicationFiled: April 16, 2018Publication date: August 16, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jinchang ZHOU, Yusheng LIN, Mingjiao LIU
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Patent number: 9972607Abstract: A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.Type: GrantFiled: August 8, 2016Date of Patent: May 15, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jinchang Zhou, Yusheng Lin, Mingjiao Liu
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Publication number: 20180040593Abstract: A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.Type: ApplicationFiled: August 8, 2016Publication date: February 8, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jinchang ZHOU, Yusheng LIN, Mingjiao LIU
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Publication number: 20180005927Abstract: A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.Type: ApplicationFiled: August 30, 2017Publication date: January 4, 2018Applicant: Semiconductor Components Industries, LLCInventors: Chun-Li Liu, Ali Salih, Balaji Padmanabhan, Mingjiao Liu