Patents by Inventor Mingrui Zhu
Mingrui Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10425262Abstract: Methods and systems are provided for adaptive guard interval (GI) combining. A signal carrying a symbol that is preceded by a guard interval (GI) that includes a portion of the symbol may be received, and a portion of the GI that is free from inter-symbol interference (ISI) may be determined. Only a part of the ISI-free portion of the GI may be selected. The selected part of the ISI-free portion of the GI may be less than a whole of the ISI-free portion. The selection may be configured based on a parameter that is applied to a function used in extracting the symbol. The parameter may be a timing adjustment, relative to a start of the symbol, applied to the function when extracting the symbol. Only the part of the ISI-free portion of the GI may then be extracted and combined with a corresponding portion of the symbol.Type: GrantFiled: August 27, 2018Date of Patent: September 24, 2019Assignee: MAXLINEAR, INC.Inventors: Mingrui Zhu, Arun Kedambadi, Seung Chul Hong, Anand Anandakumar
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Patent number: 10326462Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals.Type: GrantFiled: October 8, 2018Date of Patent: June 18, 2019Assignee: Maxlinear, Inc.Inventors: Pawandeep Taluja, Mingrui Zhu, Xuefeng Chen, Anand Anandakumar, Sheng Ye, Timothy Gallagher
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Publication number: 20190123946Abstract: Methods and systems are provided for adaptive guard interval (GI) combining. A signal carrying a symbol that is preceded by a guard interval (GI) that includes a portion of the symbol may be received, and a portion of the GI that is free from inter-symbol interference (ISI) may be determined. Only a part of the ISI-free portion of the GI may be selected. The selected part of the ISI-free portion of the GI may be less than a whole of the ISI-free portion. The selection may be configured based on a parameter that is applied to a function used in extracting the symbol. The parameter may be a timing adjustment, relative to a start of the symbol, applied to the function when extracting the symbol. Only the part of the ISI-free portion of the GI may then be extracted and combined with a corresponding portion of the symbol.Type: ApplicationFiled: August 27, 2018Publication date: April 25, 2019Inventors: Mingrui Zhu, Arun Kedambadi, Seung Chul Hong, Anand Anandakumar
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Publication number: 20190044525Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals.Type: ApplicationFiled: October 8, 2018Publication date: February 7, 2019Inventors: Pawandeep Taluja, Mingrui Zhu, Xuefeng Chen, Anand Anandakumar, Sheng Ye, Timothy Gallagher
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Patent number: 10097193Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals.Type: GrantFiled: November 14, 2017Date of Patent: October 9, 2018Assignee: Maxlinear, Inc.Inventors: Pawandeep Taluja, Mingrui Zhu, Xuefeng Chen, Anand Anandakumar, Sheng Ye, Timothy Gallagher
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Patent number: 10069514Abstract: Methods and systems are provided for low-power decoding. An example system may include one or more storage circuits and a decoder circuit. The decoder circuit may implement a plurality of nodes for use during decoding, including at least one data generating node and at least one data checking node, and the storage circuits may store status information associated with the nodes, the status information indicating when each corresponding node is locked or unlocked. During decoding operations, the decoder circuit may set the status information to lock one or more of the nodes based on one or more locking conditions, and may cease decoding based on one or more ceasing conditions. The decoder circuit may locks a data generating node when a corresponding calculated value meets a particular condition, and may lock a data checking node when all data generating nodes associated with it are locked.Type: GrantFiled: December 5, 2017Date of Patent: September 4, 2018Assignee: MAXLINEAR, INC.Inventors: Mingrui Zhu, Curtis Ling, Timothy Gallagher
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Patent number: 10063399Abstract: Methods and systems are provided for adaptive guard interval (GI) combining. When a signal carrying at least one symbol that is preceded by a guard interval that comprises a portion of the symbol is received, a portion of the guard interval that is free from inter-symbol interference (ISI) may be determined, and only a part of the ISI-free portion of the guard interval may be extracted. The part of the ISI-free portion of the guard interval may be selected based on timing adjustment, relative to start of the symbol, that is applied to a function used in extracting the symbol. The extracted part of the ISI-free portion of the guard interval may then be combined with a corresponding portion of the symbol. The extracting and/or combining may be performed after a determination that a delay spread is smaller than a predetermined channel delay.Type: GrantFiled: April 15, 2015Date of Patent: August 28, 2018Assignee: MAXLINEAR, INC.Inventors: Mingrui Zhu, Arun Kedambadi, Seung Chul Hong, Anand Anandakumar
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Publication number: 20180159554Abstract: In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.Type: ApplicationFiled: December 5, 2017Publication date: June 7, 2018Inventors: Mingrui Zhu, Curtis Ling, Timothy Gallagher
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Publication number: 20180069562Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals.Type: ApplicationFiled: November 14, 2017Publication date: March 8, 2018Inventors: Pawandeep Taluja, Mingrui Zhu, Xuefeng Chen, Anand Anandakumar, Sheng Ye, Timothy Gallagher
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Patent number: 9838035Abstract: In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.Type: GrantFiled: November 22, 2016Date of Patent: December 5, 2017Assignee: MaxLinear, Inc.Inventors: Mingrui Zhu, Curtis Ling, Timothy Gallagher
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Patent number: 9825640Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals.Type: GrantFiled: February 17, 2017Date of Patent: November 21, 2017Assignee: Maxlinear, Inc.Inventors: Pawandeep Taluja, Mingrui Zhu, Xuefeng Chen, Anand Anandakumar, Sheng Ye, Timothy Leo Gallagher
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Publication number: 20170163277Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals.Type: ApplicationFiled: February 17, 2017Publication date: June 8, 2017Inventors: Pawandeep Taluja, Mingrui Zhu, Xuefeng Chen, Anand Anandakumar, Sheng Ye, Timothy Leo Gallagher
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Publication number: 20170077953Abstract: In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.Type: ApplicationFiled: November 22, 2016Publication date: March 16, 2017Inventors: Mingrui Zhu, Curtis Ling, Timothy Gallagher
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Patent number: 9577655Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.Type: GrantFiled: October 22, 2015Date of Patent: February 21, 2017Assignee: Maxlinear, Inc.Inventors: Pawandeep Taluja, Mingrui Zhu, Xuefeng Chen, Anand Anandakumar, Sheng Ye, Timothy Leo Gallagher
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Patent number: 9509340Abstract: In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.Type: GrantFiled: March 21, 2016Date of Patent: November 29, 2016Assignee: Maxlinear, Inc.Inventors: Mingrui Zhu, Curtis Ling, Timothy Gallagher
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Publication number: 20160204802Abstract: In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.Type: ApplicationFiled: March 21, 2016Publication date: July 14, 2016Inventors: Mingrui Zhu, Curtis Ling, Timothy Gallagher
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Patent number: 9294129Abstract: In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.Type: GrantFiled: January 16, 2014Date of Patent: March 22, 2016Assignee: MaxLinear, Inc.Inventors: Mingrui Zhu, Curtis Ling, Timothy Gallagher
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Publication number: 20160043731Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.Type: ApplicationFiled: October 22, 2015Publication date: February 11, 2016Inventors: Pawandeep Taluja, Mingrui Zhu, Xuefeng Chen, Anand Anandakumer, Sheng Ye, Timothy Leo Gallagher
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Patent number: 9172386Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.Type: GrantFiled: January 6, 2015Date of Patent: October 27, 2015Assignee: Maxlinear, Inc.Inventors: Pawandeep Taluja, Mingrui Zhu, Xuefeng Chen, Anand Anandakumar, Sheng Ye, Timothy Leo Gallagher
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Publication number: 20150222466Abstract: Methods and systems are provided for adaptive guard interval (GI) combining. When a signal carrying at least one symbol that is preceded by a guard interval that comprises a portion of the symbol is received, a portion of the guard interval that is free from inter-symbol interference (ISI) may be determined, and only a part of the ISI-free portion of the guard interval may be extracted. The part of the ISI-free portion of the guard interval may be selected based on timing adjustment, relative to start of the symbol, that is applied to a function used in extracting the symbol. The extracted part of the ISI-free portion of the guard interval may then be combined with a corresponding portion of the symbol. The extracting and/or combining may be performed after a determination that a delay spread is smaller than a predetermined channel delay.Type: ApplicationFiled: April 15, 2015Publication date: August 6, 2015Inventors: Mingrui Zhu, Arun Kedambadi, Seung Chul Hong, Anand Anandakumar