Abstract: A semiconductor package including a first package substrate, a first semiconductor chip on a top surface of the first package substrate, an interposer electrically connected to the first package substrate on a top surface of the first semiconductor chip, and a molding layer configured to cover the first package substrate and the first semiconductor chip may be provided. The interposer may include an interposer trench recessed from a bottom surface of the interposer that faces both the top surface of the first semiconductor chip and the top surface of the first package substrate, and an interposer hole penetrating the interposer. The molding layer may include a filling portion filling a region between the first package substrate and the interposer, a through portion filling the interposer hole, and a cover portion covering at least a part of a top surface of the interposer.

Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.

Abstract: A semiconductor package includes: a wiring structure including at least one wiring layer; a semiconductor chip disposed on the wiring structure and connected to the wiring structure; a connecting terminal formed on a first surface of the wiring structure; a support member spaced apart from the wiring structure; a dummy connecting terminal formed on a first surface of the support member; and a mold layer covering a side surface of the wiring structure, a first surface of the semiconductor chip, and a second surface and a side surface of the support member.

Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.

Abstract: A bonding apparatus includes a body part; a vacuum hole disposed in the body part; a first protruding part protruding in a first direction from a first surface of the body part; a second protruding part protruding from the first surface of the body part in the first direction and spaced farther apart from a center of the first surface of the body part than the first protruding part in a second direction intersecting with the first direction; and a trench defined by the first surface of the body part and second surfaces of the first protruding part, the second surfaces protruding in the first direction from the first surface of the body part, and the trench being connected to the vacuum hole, wherein the second protruding part protrudes farther from the first surface of the body part in the first direction than the first protruding part.

Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.

Abstract: A semiconductor package including a first package substrate, a first semiconductor chip on a top surface of the first package substrate, an interposer electrically connected to the first package substrate on a top surface of the first semiconductor chip, and a molding layer configured to cover the first package substrate and the first semiconductor chip may be provided. The interposer may include an interposer trench recessed from a bottom surface of the interposer that faces both the top surface of the first semiconductor chip and the top surface of the first package substrate, and an interposer hole penetrating the interposer. The molding layer may include a filling portion filling a region between the first package substrate and the interposer, a through portion filling the interposer hole, and a cover portion covering at least a part of a top surface of the interposer.

Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.

Abstract: A bonding apparatus includes a body part; a vacuum hole disposed in the body part; a first protruding part protruding in a first direction from a first surface of the body part; a second protruding part protruding from the first surface of the body part in the first direction and spaced farther apart from a center of the first surface of the body part than the first protruding part in a second direction intersecting with the first direction; and a trench defined by the first surface of the body part and second surfaces of the first protruding part, the second surfaces protruding in the first direction from the first surface of the body part, and the trench being connected to the vacuum hole, wherein the second protruding part protrudes farther from the first surface of the body part in the first direction than the first protruding part.

Abstract: A semiconductor device includes a semiconductor substrate including an in-cell area and a scribe lane defining the in-cell area, a first overlay pattern on the semiconductor substrate, and a second overlay pattern adjacent to the first overlay pattern, wherein the first overlay pattern is a diffraction-based overlay (DBO) pattern and the second overlay pattern is a scanning electron microscope (SEM) overlay pattern.

Abstract: A semiconductor device includes a first overlay group and a second overlay group disposed on a semiconductor substrate. The first overlay group includes first lower overlay patterns which extend in a first direction, first upper overlay patterns overlapping the first lower overlay patterns, and first via overlay patterns interposed between the first lower overlay patterns and the first upper overlay patterns. The second overlay group includes second lower overlay patterns which extend in a second direction, second upper overlay patterns overlapping the second lower overlay patterns, and second via overlay patterns interposed between the second lower overlay patterns and the second upper overlay patterns. The second lower overlay patterns include end portions adjacent to and spaced apart from the first overlay group.

Abstract: A semiconductor device includes a semiconductor substrate including an in-cell area and a scribe lane defining the in-cell area, a first overlay pattern on the semiconductor substrate, and a second overlay pattern adjacent to the first overlay pattern, wherein the first overlay pattern is a diffraction-based overlay (DBO) pattern and the second overlay pattern is a scanning electron microscope (SEM) overlay pattern.

Abstract: A semiconductor device includes a first overlay group and a second overlay group disposed on a semiconductor substrate. The first overlay group includes first lower overlay patterns which extend in a first direction, first upper overlay patterns overlapping the first lower overlay patterns, and first via overlay patterns interposed between the first lower overlay patterns and the first upper overlay patterns. The second overlay group includes second lower overlay patterns which extend in a second direction, second upper overlay patterns overlapping the second lower overlay patterns, and second via overlay patterns interposed between the second lower overlay patterns and the second upper overlay patterns. The second lower overlay patterns include end portions adjacent to and spaced apart from the first overlay group.

Abstract: A method for making a semiconductor device includes forming a trench in a first layer on a substrate. A conductive layer having a pattern is formed in the trench. A first metal gate electrode is formed on the conductive layer, and a second metal gate electrode is formed on the first metal gate electrode. The first and second metal gate electrodes at least partially conform to the pattern of the conductive layer. Widths of first surfaces of the first and second metal gate electrodes are different from respective widths of second surfaces of the first and second metal gate electrodes as a result of the pattern.

Abstract: A method for making a semiconductor device includes forming a trench in a first layer on a substrate. A conductive layer having a pattern is formed in the trench. A first metal gate electrode is formed on the conductive layer, and a second metal gate electrode is formed on the first metal gate electrode. The first and second metal gate electrodes at least partially conform to the pattern of the conductive layer. Widths of first surfaces of the first and second metal gate electrodes are different from respective widths of second surfaces of the first and second metal gate electrodes as a result of the pattern.

Abstract: A substrate including internal interconnections, first and second finger electrodes, and having first to fourth quadrants. External terminals are formed on the substrate and connected to the first and second finger electrodes via the internal interconnections. A first tower including first semiconductor chips is formed on the substrate. First conductive wires are formed between the first semiconductor chips and the first finger electrodes. A second tower including second semiconductor chips is formed on the substrate. Second conductive wires are formed between the second semiconductor chips and the second finger electrodes. The external terminals include a first group connected to the first finger electrodes and configuring a channel, and a second group connected to the second finger electrodes, and configuring another channel. The first finger electrodes are formed on the third quadrant, and the second finger electrodes are formed on the first quadrant.

Abstract: Provided are a semiconductor package and a method for forming the same, and a PCB (printed circuit board). The semiconductor package comprises: a PCB including a slit at a substantially central portion thereof, the PCB including an upper surface and a lower surface; a semiconductor chip mounted on the upper surface of the PCB; an upper molding layer disposed on the upper surface and covering the semiconductor chip; and a lower molding layer filling the slit and covering a portion of the lower surface of the PCB, wherein the PCB comprises a connecting recess at a side surface thereof, and the upper molding layer and the lower molding layer are in contact with each other at the connecting recess.

Abstract: A bonding pad structure for a semiconductor device includes a first lower metal layer beneath a second upper metal layer in a bonding region of the device. The lower metal layer is formed such that the metal of the lower metal layer is absent from the bonding region. As a result, if damage occurs to the structure during procedures such as probing or bonding at the bonding region, the lower metal is not exposed to the environment. Oxidation of the lower metal layer by exposure to the environment is prevented, thus improving reliability of the device.

Abstract: A ball grid array (BGA) package that may suppress flash contamination may include a flash contamination barrier wall. The barrier wall may be a portion of a copper pattern provided on a substrate. During a molding process, the flash contamination barrier may prevent a flash from contaminating a ball land. The barrier wall may restrict the flash to flow through a concave portion that may be defined by a surface of the substrate.

Abstract: A semiconductor wafer includes a plurality of unitary semiconductor chips formed on a semiconductor substrate. Scribe lane region separate the unitary semiconductor chips from each other. Test element group (TEG) pads are configured to apply testing signals for testing respective test elements. A TEG pad is arranged such that an acute angle formed at an intersection of a line extending from portion of a perimeter of the TEG pad and at least a portion of the outer edge of a corresponding scribe lane region is greater than 0° and less than or equal to 60°.