Patents by Inventor Minoru Ikarashi

Minoru Ikarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8680502
    Abstract: A memory device includes: first and second electrodes; a semiconductor layer of a first conduction type provided on the first electrode side; a solid electrolyte layer containing movable ions and provided on the second electrode side; and an amorphous semiconductor layer of a second conduction type which is provided between the semiconductor layer and the solid electrolyte layer so as to be in contact with the solid electrolyte layer and, at the time of application of voltage to the first and second electrodes, reversibly changes to the first conduction type.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: March 25, 2014
    Assignee: Sony Corporation
    Inventors: Minoru Ikarashi, Katsuhisa Aratani
  • Patent number: 8659000
    Abstract: A memory device includes: an amorphous semiconductor layer of a first conduction type; a solid electrolyte layer containing movable ions and provided in contact with a part of one of faces of the amorphous semiconductor layer; a first electrode electrically connected to the amorphous semiconductor layer via the solid electrolyte layer; a second electrode electrically connected to one of the faces of the amorphous semiconductor layer; and a third electrode provided over the other face of the amorphous semiconductor layer with an insulating layer therebetween. At the time of application of voltage to the third electrode, at least a part of the amorphous semiconductor layer reversibly changes to a second conduction type.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: February 25, 2014
    Assignee: Sony Corporation
    Inventors: Minoru Ikarashi, Katsuhisa Aratani
  • Publication number: 20130334489
    Abstract: A storage device includes: a first electrode; a storage layer including an ion source layer; and a second electrode. The first electrode, the storage layer, and the second electrode are provided in this order. The ion source layer contains a movable element, and has a volume resistivity of about 150 m?·cm to about 12000 m?·cm both inclusive.
    Type: Application
    Filed: June 7, 2013
    Publication date: December 19, 2013
    Inventors: HIROAKI SEI, KAZUHIRO OHBA, TAKEYUKI SONE, MINORU IKARASHI
  • Publication number: 20130256622
    Abstract: A storage device includes: a first electrode; a storage layer including an ion source layer; and a second electrode. The first electrode, the storage layer, and the second electrode are provided in this order. The ion source layer includes a chalcogen element, oxygen, and one or more transition metal elements selected from the group of Groups 4, 5, and 6 elements of the Periodic Table.
    Type: Application
    Filed: March 22, 2013
    Publication date: October 3, 2013
    Applicant: Sony Corporation
    Inventors: Hiroaki Sei, Kazuhiro Ohba, Takeyuki Sone, Minoru Ikarashi
  • Patent number: 8437180
    Abstract: A memory includes: a memory device that has a memory layer storing data as a magnetization state of a magnetic body and a magnetization fixed layer whose direction of magnetization is fixed through a nonmagnetic layer interposed between the memory layer and the magnetization fixed layer and stores the data in the memory layer by changing a magnetization direction of the memory layer when a write current flowing in a stacked direction of the memory layer and the magnetization fixed layer is applied; and a voltage control unit that supplies the write current configured by independent pulse trains of two or more to the memory device by using a write voltage that is configured by independent pulse trains of two or more.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: May 7, 2013
    Assignee: Sony Corporation
    Inventors: Yutaka Higo, Masanori Hosomi, Minoru Ikarashi, Hiroshi Kano, Shinichiro Kusunoki, Hiroyuki Ohmori, Yuki Oishi, Kazutaka Yamane, Tetsuya Yamamoto, Kazuhiro Bessho
  • Patent number: 8339840
    Abstract: A memory is provided that is capable of improving the thermal stability without increasing the write current. The memory is configured to include: a storage element which has a storage layer that holds information according to a magnetization state of a magnetic substance and in which a magnetization fixed layer is provided on the storage layer with an intermediate layer 16 interposed therebetween, the intermediate layer is formed of an insulator, the direction of magnetization of the storage layer is changed by injecting electrons spin-polarized in a lamination direction such that the information is recorded in the storage layer, and distortion is applied to the storage layer from an insulating layer which exists around the storage layer and has a smaller coefficient of thermal expansion than the storage layer. A wiring line for supplying a current flowing in the lamination direction of the storage element.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: December 25, 2012
    Assignee: Sony Corporation
    Inventors: Masanori Hosomi, Hiroyuki Ohmori, Minoru Ikarashi, Tetsuya Yamamoto, Yutaka Higo, Kazutaka Yamane, Yuki Oishi, Hiroshi Kano
  • Patent number: 8331136
    Abstract: A recording method of a nonvolatile memory including a recording circuit that electrically performs recording of information for an information memory device having a resistance change connected to a power supply for information recording, includes the steps of: recording information in a low-resistance state by the recording circuit under a condition that an output impedance of the recording circuit for the information memory device is larger than a resistance value in the low-resistance state of the information memory device; and recording information in a high-resistance state by the recording circuit under a condition that an output impedance of the recording circuit for the information memory device is smaller than a resistance value in the high-resistance state of the information memory device.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: December 11, 2012
    Assignee: Sony Corporation
    Inventors: Hiroyuki Ohmori, Tetsuya Yamamoto, Masanori Hosomi, Yutaka Higo, Kazutaka Yamane, Kazuhiro Bessho, Hiroshi Kano, Minoru Ikarashi, Yuki Oishi, Shinichiro Kusunoki
  • Patent number: 8194443
    Abstract: A memory device includes: a memory layer that retains information based on a magnetization state of a magnetic material, a first intermediate layer and a second intermediate layer that are provided to sandwich the memory layer and are each formed of an insulator, a first fixed magnetic layer disposed on an opposite side of the first intermediate layer from the memory layer, a second fixed magnetic layer disposed on an opposite side of the second intermediate layer from the memory layer, and a nonmagnetic conductive layer provided between either the first intermediate layer or the second intermediate layer and the memory layer, the memory device being configured so that spin-polarized electrons are injected thereinto in a stacking direction to change the magnetization direction of the memory layer, thereby storing information in the memory layer.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: June 5, 2012
    Assignee: Sony Corporation
    Inventors: Kazutaka Yamane, Masanori Hosomi, Hiroshi Kano, Hiroyuki Ohmori, Minoru Ikarashi, Tetsuya Yamamoto, Kazuhiro Bessho, Yutaka Higo, Yuki Oishi, Shinichiro Kusunoki
  • Patent number: 8169818
    Abstract: A recording method for a magnetic memory device that includes applying, when recording one piece of information, one or more main pulses and one or more sub-pulses in the same direction and applying the one or more sub-pulses after the one or more main pulses, the one or more main pulses each being a pulse that has a sufficient pulse height and pulse width to record information, the one or more sub-pulses each being a pulse that satisfies at least one of conditions that a pulse width is shorter than that of the one or more main pulses and that a pulse height is smaller than that of the one or more main pulses.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: May 1, 2012
    Assignee: Sony Corporation
    Inventors: Hiroyuki Ohmori, Masanori Hosomi, Minoru Ikarashi, Tetsuya Yamamoto, Kazutaka Yamane, Yuki Oishi, Hiroshi Kano
  • Patent number: 8149613
    Abstract: A resistance variable memory device is provided and includes a resistance variable memory cell that writes data by utilizing a spin transfer effect based on an injection current. The memory device also includes a driving circuit that generates a combined pulse of a plurality of write pulses and an offset pulse defining the level between the write pulses and supplies the combined pulse to the memory cell at the time of the writing.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: April 3, 2012
    Assignee: Sony Corporation
    Inventors: Minoru Ikarashi, Yutaka Higo, Masanori Hosomi, Hiroshi Kano, Shinichiro Kusunoki, Hiroyuki Ohmori, Yuki Oishi, Tetsuya Yamamoto, Kazutaka Yamane
  • Publication number: 20120037872
    Abstract: A memory device includes: an amorphous semiconductor layer of a first conduction type; a solid electrolyte layer containing movable ions and provided in contact with a part of one of faces of the amorphous semiconductor layer; a first electrode electrically connected to the amorphous semiconductor layer via the solid electrolyte layer; a second electrode electrically connected to one of the faces of the amorphous semiconductor layer; and a third electrode provided over the other face of the amorphous semiconductor layer with an insulating layer therebetween. At the time of application of voltage to the third electrode, at least a part of the amorphous semiconductor layer reversibly changes to a second conduction type.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 16, 2012
    Applicant: SONY CORPORATION
    Inventors: Minoru Ikarashi, Katsuhisa Aratani
  • Publication number: 20120037873
    Abstract: A memory device includes: first and second electrodes; a semiconductor layer of a first conduction type provided on the first electrode side; a solid electrolyte layer containing movable ions and provided on the second electrode side; and an amorphous semiconductor layer of a second conduction type which is provided between the semiconductor layer and the solid electrolyte layer so as to be in contact with the solid electrolyte layer and, at the time of application of voltage to the first and second electrodes, reversibly changes to the first conduction type.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 16, 2012
    Applicant: SONY CORPORATION
    Inventors: Minoru Ikarashi, Katsuhisa Aratani
  • Patent number: 8089802
    Abstract: Disclosed is a memory device including a memory layer retaining information thereon based on a magnetization state of a magnetic body, a fixed-magnetization layer having a fixed-magnetization direction formed on the memory layer through a non-magnetic layer, and two metal wiring lines formed adjacent to both ends of the fixed-magnetization layer. In the memory, the magnetization direction of the memory layer is changed by passing an electric current therethrough in a stacked direction to record the information on the memory layer.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: January 3, 2012
    Assignee: Sony Corporation
    Inventors: Yutaka Higo, Minoru Ikarashi, Masanori Hosomi, Hiroyuki Ohmori, Tetsuya Yamamoto, Kazutaka Yamane, Yuki Oishi, Hiroshi Kano
  • Patent number: 8072789
    Abstract: A resistance-change memory device is provided and includes a stack constituting a tunnel magnetoresistance effect element that has a magnetic layer in which a direction of magnetization is switchable and that is formed on a conductive layer, and the stack is included in a resistance-change memory cell performing data writing utilizing a spin transfer effect caused by current injection. The stack is formed such that a line connecting centers of respective layers of the stack is tilted with respect to a direction perpendicular to a surface of the conductive layer having the stack formed thereon.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: December 6, 2011
    Assignee: Sony Corporation
    Inventors: Minoru Ikarashi, Yutaka Higo, Masanori Hosomi, Hiroshi Kano, Shinichiro Kusunoki, Hiroyuki Ohmori, Yuki Oishi, Tetsuya Yamamoto, Kazutaka Yamane
  • Patent number: 8018759
    Abstract: A memory includes: a plurality of memory devices, each including a tunnel magnetic resistance effect device containing a magnetization free layer in which a direction of magnetization can be reversed, a tunnel barrier layer including an insulating material, and a magnetization fixed layer provided with respect to the magnetization free layer via the tunnel barrier layer with a fixed direction of magnetization; a random access memory area in which information is recorded using the direction of magnetization of the magnetization free layer of the memory device; and a read only memory area in which information is recorded depending on whether there is breakdown of the tunnel barrier layer of the memory device or not.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: September 13, 2011
    Assignee: Sony Corporation
    Inventors: Hiroshi Kano, Yutaka Higo, Tetsuya Yamamoto, Hiroyuki Ohmori, Masanori Hosomi, Shinichiro Kusunoki, Yuki Oishi, Kazutaka Yamane, Kazuhiro Bessho, Minoru Ikarashi
  • Publication number: 20110032744
    Abstract: [Object] To provide a recording method for a magnetic memory device including a recording layer that holds information as a magnetization direction of a magnetic body and a magnetization reference layer that is provided with respect to the recording layer with an insulation layer interposed therebetween, the magnetic memory device being recorded with information by a current flowing between the recording layer and the magnetization reference layer via the insulation layer, the recording method being capable of maintaining, even when a write pulse considerably higher than an inversion threshold value is applied, the same level of error rate as in a case where a write pulse a little higher than the inversion threshold value is applied.
    Type: Application
    Filed: April 15, 2009
    Publication date: February 10, 2011
    Applicant: SONY CORPORATION
    Inventors: Hiroyuki Ohmori, Masanori Hosomi, Minoru Ikarashi, Tetsuya Yamamoto, Kazutaka Yamane, Yuki Oishi, Hiroshi Kano
  • Patent number: 7881097
    Abstract: Disclosed is a storage element having a storage layer retaining information based on a magnetization state of a magnetic material; a fixed-magnetization layer having a ferromagnetic layer; and an intermediate layer interposed between the storage layer and the fixed-magnetization layer. In the storage element, spin-polarized electrons are injected in a stacking direction to change a magnetization direction of the storage layer so that information is recorded in the storage layer, and resistivity of the ferromagnetic layer forming the storage layer is 8×10?7 ?m or more.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: February 1, 2011
    Assignee: Sony Corporation
    Inventors: Masanori Hosomi, Hiroyuki Ohmori, Minoru Ikarashi, Tetsuya Yamamoto, Yutaka Higo, Kazutaka Yamane, Yuki Oishi, Hiroshi Kano
  • Publication number: 20100328998
    Abstract: A memory includes: a memory device that has a memory layer storing data as a magnetization state of a magnetic body and a magnetization fixed layer whose direction of magnetization is fixed through a nonmagnetic layer interposed between the memory layer and the magnetization fixed layer and stores the data in the memory layer by changing a magnetization direction of the memory layer when a write current flowing in a stacked direction of the memory layer and the magnetization fixed layer is applied; and a voltage control unit that supplies the write current configured by independent pulse trains of two or more to the memory device by using a write voltage that is configured by independent pulse trains of two or more.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 30, 2010
    Applicant: SONY CORPORATION
    Inventors: Yutaka Higo, Masanori Hosomi, Minoru Ikarashi, Hiroshi Kano, Shinichiro Kusunoki, Hiroyuki Ohmori, Yuki Oishi, Kazutaka Yamane, Tetsuya Yamamoto, Kazuhiro Bessho
  • Publication number: 20100328993
    Abstract: A recording method of a nonvolatile memory including a recording circuit that electrically performs recording of information for an information memory device having a resistance change connected to a power supply for information recording, includes the steps of: recording information in a low-resistance state by the recording circuit under a condition that an output impedance of the recording circuit for the information memory device is larger than a resistance value in the low-resistance state of the information memory device; and recording information in a high-resistance state by the recording circuit under a condition that an output impedance of the recording circuit for the information memory device is smaller than a resistance value in the high-resistance state of the information memory device.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 30, 2010
    Applicant: SONY CORPORATION
    Inventors: Hiroyuki Ohmori, Tetsuya Yamamoto, Masanori Hosomi, Yutaka Higo, Kazutaka Yamane, Kazuhiro Bessho, Hiroshi Kano, Minoru Ikarashi, Yuki Oishi, Shinichiro Kusunoki
  • Publication number: 20100328992
    Abstract: A memory includes: a plurality of memory devices, each including a tunnel magnetic resistance effect device containing a magnetization free layer in which a direction of magnetization can be reversed, a tunnel barrier layer including an insulating material, and a magnetization fixed layer provided with respect to the magnetization free layer via the tunnel barrier layer with a fixed direction of magnetization; a random access memory area in which information is recorded using the direction of magnetization of the magnetization free layer of the memory device; and a read only memory area in which information is recorded depending on whether there is breakdown of the tunnel barrier layer of the memory device or not.
    Type: Application
    Filed: June 17, 2010
    Publication date: December 30, 2010
    Applicant: SONY CORPORATION
    Inventors: Hiroshi Kano, Yutaka Higo, Tetsuya Yamamoto, Hiroyuki Ohmori, Masanori Hosomi, Shinichiro Kusunoki, Yuki Oishi, Kazutaka Yamane, Kazuhiro Bessho, Minoru Ikarashi