Patents by Inventor Minoru Ishida

Minoru Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031429
    Abstract: The present disclosure relates to a semiconductor device, a solid-state image pickup element, an image pickup device, and an electronic apparatus that are enabled to reduce restrictions on materials and restrictions on device configuration. A CSP imager and a mounting substrate are connected together with a connection portion other than a solder ball. With such a configuration, restrictions on materials and restrictions on device configuration are reduced, which has conventionally occurred because it is limited to a configuration in which solder balls are used for connection. The present disclosure can be applied to image pickup devices.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: June 8, 2021
    Assignee: Sony Corporation
    Inventors: Yoshiaki Masuda, Minoru Ishida
  • Publication number: 20210134861
    Abstract: The present disclosure relates to reducing the size of a solid-state imaging apparatus. The solid-state imaging apparatus is configured by laminating a first structure body, comprising a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned, and a second structure body, comprising an output circuit unit for outputting a pixel signal. The output circuit unit, including a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit.
    Type: Application
    Filed: January 13, 2021
    Publication date: May 6, 2021
    Applicant: SONY CORPORATION
    Inventors: Harumi TANAKA, Yoshiaki MASUDA, Shinji MIYAZAWA, Minoru ISHIDA
  • Patent number: 10998556
    Abstract: The present invention relates to a catalyst for a solid polymer fuel cell, including platinum, cobalt, and zirconium supported as a catalytic metal on a carbon powder carrier, in which the supporting ratio of platinum, cobalt, and zirconium on the carbon powder carrier is Pt:Co:Zr=3:0.5 to 1.5:0.1 to 3.0 by molar ratio. In the present invention, it is preferable that the peak position of Pt3Co seen in the X-ray diffraction pattern of catalyst particles is 2?=41.10° or more and 42.00° or less, and moderate alloying has occurred in the catalytic metal.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 4, 2021
    Assignee: TANAKA KIKINZOKU KOGYO K.K.
    Inventors: Wataru Hashimoto, Tatsunori Namai, Minoru Ishida, Hitoshi Nakajima, Kazuki Okaya, Takeshi Kaieda, Koichi Matsutani
  • Patent number: 10998369
    Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 4, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
  • Publication number: 20210104571
    Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.
    Type: Application
    Filed: March 23, 2018
    Publication date: April 8, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Reijiroh SHOHJI, Masaki HANEDA, Hiroshi HORIKOSHI, Minoru ISHIDA, Takatoshi KAMESHIMA, Ikue MITSUHASHI, Hideto HASHIGUCHI, Tadashi IIJIMA
  • Publication number: 20210104570
    Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance.
    Type: Application
    Filed: March 23, 2018
    Publication date: April 8, 2021
    Inventors: IKUE MITSUHASHI, REIJIROH SHOHJI, MINORU ISHIDA, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, HIROSHI HORIKOSHI, MASAKI HANEDA
  • Publication number: 20210104572
    Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line in another wiring layer.
    Type: Application
    Filed: March 23, 2018
    Publication date: April 8, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takatoshi KAMESHIMA, Hideto HASHIGUCHI, Ikue MITSUHASHI, Hiroshi HORIKOSHI, Reijiroh SHOHJI, Minoru ISHIDA, Tadashi IIJIMA, Masaki HANEDA
  • Publication number: 20210084249
    Abstract: An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.
    Type: Application
    Filed: December 27, 2018
    Publication date: March 18, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Keiichi NAKAZAWA, Yoshiaki KITANO, Hirofumi YAMASHITA, Minoru ISHIDA
  • Patent number: 10923517
    Abstract: The present disclosure relates to reducing the size of a solid-state imaging apparatus. The solid-state imaging apparatus is configured by laminating a first structure body, comprising a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned, and a second structure body, comprising an output circuit unit for outputting a pixel signal. The output circuit unit, including a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: February 16, 2021
    Assignee: Sony Corporation
    Inventors: Harumi Tanaka, Yoshiaki Masuda, Shinji Miyazawa, Minoru Ishida
  • Patent number: 10903503
    Abstract: The present invention is a catalyst for a solid polymer fuel cell including: catalyst particles of platinum, cobalt and manganese; and a carbon powder carrier supporting the catalyst particles, wherein the component ratio (molar ratio) of the platinum, cobalt and manganese of the catalyst particles is of Pt:Co:Mn=1:0.06 to 0.39:0.04 to 0.33, and wherein in an X-ray diffraction analysis of the catalyst particles, the peak intensity ratio of a Co—Mn alloy appearing around 2?=27° is 0.15 or less on the basis of a main peak appearing around 2?=40°. It is particularly preferred that the catalyst have a peak ratio of a peak of a CoPt3 alloy and an MnPt3 alloy appearing around 2?=32° of 0.14 or more on the basis of a main peak.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: January 26, 2021
    Assignee: TANAKA KIKINZOKU KOGYO K.K.
    Inventors: Minoru Ishida, Koichi Matsutani
  • Patent number: 10892496
    Abstract: The present invention provides a catalyst for a solid polymer fuel cell, having excellent initial activity and good durability and a production method thereof. The present invention is a catalyst for a solid polymer fuel cell, including catalyst particles composed of platinum or a platinum alloy supported on a carbon powder carrier, the catalyst having sulfo groups (—SO3H) at least on the catalyst particles, and the catalyst further having a fluorine compound having a C—F bond supported at least on the catalyst particles. It is preferred in the catalyst of the present invention that sulfur content is 800 ppm or more and 5000 ppm or less based on the mass of the whole catalyst and the amount of the fluorine compound is 3 mass % or more and 24 mass % or less based on the mass of the whole catalyst.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: January 12, 2021
    Assignee: TANAKA KIKINZOKU KOGYO K.K.
    Inventors: Minoru Ishida, Koichi Matsutani
  • Patent number: 10886869
    Abstract: A control apparatus is applied to a vehicle including (i) a rotating electrical machine and (ii) a wheel speed sensor detecting a wheel speed. The control apparatus sets a rotation angle of the rotating electrical machine based on an estimated value of the rotation angle which is estimated based on a detection value of the wheel speed sensor.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: January 5, 2021
    Assignee: DENSO CORPORATION
    Inventors: Minoru Ishida, Naoki Katayama, Tsubasa Sakuishi, Yuki Takahashi
  • Patent number: 10875418
    Abstract: In a charging control apparatus, a supply power requestor requests an external power source to output supply power having a constant voltage and a constant current. A voltage conversion instructor instructs a voltage conversion device to perform voltage conversion of the supply power from the external power source such that converted supply power has a charging voltage and a charging current that are respectively within allowable charging-voltage range and allowable charging-current range. The voltage conversion instructor instructs the voltage conversion device to output the converted supply power to the power storage to thereby charge the power storage.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: December 29, 2020
    Assignee: DENSO CORPORATION
    Inventors: Minoru Ishida, Naoki Katayama, Tsubasa Sakuishi
  • Publication number: 20200365639
    Abstract: A deformation of a stacked lens is suppressed. A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are bonded and stacked by direct bonding. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.
    Type: Application
    Filed: July 31, 2020
    Publication date: November 19, 2020
    Applicant: Sony Corporation
    Inventors: Hiroyasu MATSUGAI, Hiroyuki ITOU, Suguru SAITO, Keiji OHSHIMA, Masanori IWASAKI, Toshihiko HAYASHI, Shuzo SATO, Nobutoshi FUJII, Hiroshi TAZAWA, Toshiaki SHIRAIWA, Minoru ISHIDA
  • Publication number: 20200357838
    Abstract: Provided is a laminated lens structure capable of corresponding various optical parameters. The laminated lens structure includes at least one or more sheets of first lens-attached substrates and at least one or more sheets of second lens-attached substrates as a lens-attached substrate including a lens resin portion that forms a lens, and a carrier substrate that carries the lens resin portion. The carrier substrate of the first lens-attached substrates is constituted by laminating a plurality of sheets of carrier configuration substrates in a thickness direction, and the carrier substrate of the second lens-attached substrates is constituted by one sheet of carrier configuration substrate. For example, the present technology is applicable to a camera module and the like.
    Type: Application
    Filed: August 17, 2018
    Publication date: November 12, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Munekatsu FUKUYAMA, Hirotaka YOSHIOKA, Kunihiko HIKICHI, Atsushi YAMAMOTO, Kaori TAKIMOTO, Minoru ISHIDA
  • Patent number: 10818717
    Abstract: A deformation of a stacked lens is suppressed. A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are bonded and stacked by direct bonding. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: October 27, 2020
    Assignee: Sony Corporation
    Inventors: Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Masanori Iwasaki, Toshihiko Hayashi, Shuzo Sato, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Minoru Ishida
  • Publication number: 20200251519
    Abstract: The present disclosure relates to a semiconductor device, a solid-state image pickup element, an image pickup device, and an electronic apparatus that are enabled to reduce restrictions on materials and restrictions on device configuration. A CSP imager and a mounting substrate are connected together with a connection portion other than a solder ball. With such a configuration, restrictions on materials and restrictions on device configuration are reduced, which has conventionally occurred because it is limited to a configuration in which solder balls are used for connection. The present disclosure can be applied to image pickup devices.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Applicant: SONY CORPORATION
    Inventors: Yoshiaki MASUDA, Minoru ISHIDA
  • Publication number: 20200251511
    Abstract: The present disclosure relates to a solid-state imaging apparatus that can further downsize the size of the apparatus. The solid-state imaging apparatus is configured by laminating a first structure body, at which a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned is formed, and a second structure body, at which an output circuit unit for outputting a pixel signal outputted from the pixels to the outside of the apparatus is formed. The output circuit unit, a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the pixel array unit of the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Applicant: SONY CORPORATION
    Inventors: Harumi TANAKA, Yoshiaki MASUDA, Shinji MIYAZAWA, Minoru ISHIDA
  • Publication number: 20200243591
    Abstract: [Object] To further improve performance of a solid-state imaging device. [Solution] There is provided a solid-state imaging device including: a first substrate; a second substrate; and a third substrate that are stacked in this order. The first substrate includes a first semiconductor substrate and a first multi-layered wiring layer stacked on the first semiconductor substrate. The first semiconductor substrate has a pixel unit formed thereon. The pixel unit has pixels arranged thereon. The second substrate includes a second semiconductor substrate and a second multi-layered wiring layer stacked on the second semiconductor substrate. The second semiconductor substrate has a circuit formed thereon. The circuit has a predetermined function. The third substrate includes a third semiconductor substrate and a third multi-layered wiring layer stacked on the third semiconductor substrate. The third semiconductor substrate has a circuit formed thereon. The circuit has a predetermined function.
    Type: Application
    Filed: March 23, 2018
    Publication date: July 30, 2020
    Inventors: TADASHI IIJIMA, TAKATOSHI KAMESHIMA, IKUE MITSUHASHI, HIROSHI HORIKOSHI, HIDETO HASHIGUCHI, REIJIROH SHOHJI, MINORU ISHIDA, MASAKI HANEDA
  • Patent number: 10712543
    Abstract: A positional shift of a lens of a stacked lens structure is reduced. A plurality of through-holes is formed at a position shifted from a first target position on a substrate according to a first shift. A lens is formed on an inner side of each of the through-holes using a first mold in which a plurality of first transfer surfaces is disposed at a position shifted from a predetermined second target position according to a second shift and a second mold in which a plurality of second transfer surfaces is disposed at a position shifted from a predetermined third target position according to a third shift. The plurality of substrates having the lenses formed therein is formed according to direct bonding, and the plurality of stacked substrates is divided. The present technique can be applied to a stacked lens structure or the like, for example.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: July 14, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kunihiko Hikichi, Koichi Takeuchi, Toshihiro Kurobe, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Minoru Ishida