Patents by Inventor Minoru Ishida
Minoru Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250151448Abstract: An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.Type: ApplicationFiled: December 30, 2024Publication date: May 8, 2025Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Keiichi NAKAZAWA, Yoshiaki KITANO, Hirofumi Yamashita, Minoru ISHIDA
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Patent number: 12266675Abstract: An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.Type: GrantFiled: September 14, 2023Date of Patent: April 1, 2025Assignee: Sony Semiconductor Solutions CorporationInventors: Keiichi Nakazawa, Yoshiaki Kitano, Hirofumi Yamashita, Minoru Ishida
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Patent number: 12265040Abstract: A device for measuring the amount of moisture in a medium that includes a transmission antenna that sends a signal as an electromagnetic wave, a reception antenna that receives the electromagnetic wave sent from the transmission antenna and transmitted through a medium, a measurement section that measures the electromagnetic wave propagated to the reception antenna, and a sensor casing. The sensor device further includes a transmission substrate that includes a plurality of wiring layers and a reception substrate that includes a plurality of wiring layers, or a first covering layer that partially covers an outer periphery of the transmission substrate and a second covering layer that partially covers an outer periphery of the reception substrate The coverings are formed of an electromagnetic wave absorption material. The sensor casing includes a transmission probe casing that accommodates the transmission substrate and a reception probe casing that accommodates the reception substrate.Type: GrantFiled: November 8, 2021Date of Patent: April 1, 2025Assignees: Sony Group Corporation, Sony Semiconductor Solutions CorporationInventors: Takuya Ichihara, Norihito Mihota, Atsushi Yamada, Sachio Iida, Takahiro Oishi, Minoru Ishida
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Publication number: 20240363873Abstract: A catalyst for an oxygen reduction reaction containing catalyst particles having a shell-core structure containing a PtCo alloy or a PtCoMn alloy as a core, and platinum as a shell layer. A specific plane of a face-centered cubic lattice is formed by a plurality of platinum atoms contained in the shell layer, and a lattice constant of the plane of the face-centered cubic lattice on the catalyst particle surface is 3.70 ? or more and 4.05 ? or less (in a PtCo alloy), or 3.870 ? or more and 4.10 ? or less (in a PtCoMn alloy). A catalyst design method includes a step of calculating, with respect to an orientation plane such as the plane formed by platinum atoms of the shell layer, adsorption energies for an oxygen molecule, an OH group and a water molecule by first-principles calculation based on density functional theory.Type: ApplicationFiled: July 9, 2024Publication date: October 31, 2024Applicants: TANAKA KIKINZOKU KOGYO K.K., NATIONAL INSTITUTE OF TECHNOLOGYInventors: Minoru ISHIDA, Koichi MATSUTANI, Hiroshi NAKANISHI, Hideaki KASAI, Bhume CHANTARAMOLEE, Susan Menez ASPERA
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Publication number: 20240332335Abstract: This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.Type: ApplicationFiled: June 13, 2024Publication date: October 3, 2024Inventors: HAJIME YAMAGISHI, KIYOTAKA TABUCHI, MASAKI OKAMOTO, TAKASHI OINOUE, MINORU ISHIDA, SHOTA HIDA, KAZUTAKA YAMANE
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Patent number: 12090843Abstract: A drive control device is applicable to a vehicle including a first motor which drives a first wheel and a second motor which drives a second wheel. The drive control device includes a sensor, a torque setting section, an anomaly detection section, and an information output section. The sensor detects information about the drive control device. The torque setting section sets upper limit values of torques that can be generated by the first motor and the second motor based on the information detected by the sensor. The anomaly detection section detects an anomaly in the drive control device. In response to the anomaly detection section detecting the anomaly, the information output section outputs, to the torque setting section, setting information that sets the upper limit values of the torques of the first motor and the second motor to a common predetermined value, as the information.Type: GrantFiled: July 13, 2022Date of Patent: September 17, 2024Assignee: DENSO CORPORATIONInventors: Minoru Ishida, Harumi Horihata
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Publication number: 20240304649Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line another wiring layer.Type: ApplicationFiled: May 20, 2024Publication date: September 12, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takatoshi KAMESHIMA, Hideto HASHIGUCHI, Ikue MITSUHASHI, Hiroshi HORIKOSHI, Reijiroh SHOHJI, Minoru ISHIDA, Tadashi IIJIMA, Masaki HANEDA
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Patent number: 12080745Abstract: A solid-state imaging device is provided that comprises a first substrate that includes a first multi-layered wiring layer stacked on a first semiconductor substrate, a second substrate that includes a second multi-layered wiring layer and an insulating layer stacked on a second semiconductor substrate, and a third substrate that includes a third multi-layered wiring layer stacked on a third semiconductor substrate. A first coupling structure electrically couples the first and second substrates to each other. A second coupling structure exists on bonding surfaces of the second and third substrates, and includes an electrode junction structure in which electrodes formed on respective bonding surfaces are in direct contact with each other. A first via penetrates the second semiconductor substrate and electrically couples a first electrode to a wiring in the second multi-layered wiring layer. A second via electrically couples the second electrode to another wiring in the third multi-layered wiring layer.Type: GrantFiled: July 25, 2022Date of Patent: September 3, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
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Publication number: 20240290801Abstract: The present disclosure relates to reducing the size of a solid-state imaging apparatus. The solid-state imaging apparatus is configured by laminating a first structure body, comprising a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned, and a second structure body, comprising an output circuit unit for outputting a pixel signal. The output circuit unit, including a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit.Type: ApplicationFiled: April 5, 2024Publication date: August 29, 2024Applicant: SONY GROUP CORPORATIONInventors: Harumi TANAKA, Yoshiaki MASUDA, Shinji MIYAZAWA, Minoru ISHIDA
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Publication number: 20240274641Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.Type: ApplicationFiled: March 4, 2024Publication date: August 15, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Reijiroh SHOHJI, Masaki HANEDA, Hiroshi HORIKOSHI, Minoru ISHIDA, Takatoshi KAMESHIMA, Ikue MITSUHASHI, Hideto HASHIGUCHI, Tadashi IIJIMA
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Patent number: 12062796Abstract: A catalyst for an oxygen reduction reaction containing catalyst particles having a shell-core structure containing a PtCo alloy or a PtCoMn alloy as a core, and platinum as a shell layer. A specific plane of a face-centered cubic lattice is formed by a plurality of platinum atoms contained in the shell layer, and a lattice constant of the plane of the face-centered cubic lattice on the catalyst particle surface is 3.70 ? or more and 4.05 ? or less (in a PtCo alloy), or 3.870 ? or more and 4.10 ? or less (in a PtCoMn alloy). A catalyst design method includes a step of calculating, with respect to an orientation plane such as the plane formed by platinum atoms of the shell layer, adsorption energies for an oxygen molecule, an OH group and a water molecule by first-principles calculation based on density functional theory.Type: GrantFiled: December 13, 2021Date of Patent: August 13, 2024Assignees: TANAKA KIKINZOKU KOGYO K.K., NATIONAL INSTITUTE OF TECHNOLOGYInventors: Minoru Ishida, Koichi Matsutani, Hiroshi Nakanishi, Hideaki Kasai, Bhume Chantaramolee, Susan Menez Aspera
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Patent number: 12057462Abstract: Provided is a solid-state imaging device that includes a first substrate which includes a first semiconductor substrate and a first multi-layered wiring layer that are stacked, a second substrate which includes a second semiconductor substrate and a second multi-layered wiring layer that are stacked, and a third substrate which includes a third semiconductor substrate and a third multi-layered wiring layer that are stacked. The solid-state imaging device further includes a first coupling structure for electrically coupling a circuit of the first substrate and a circuit of the second substrate to each other. The first coupling structure includes a via in which one through hole electrically couples a predetermined wiring line in the first multi-layered wiring layer, and a predetermined wiring line in the second multi-layered wiring layer or a predetermined wiring line in the third multi-layered wiring layer to each other.Type: GrantFiled: August 9, 2021Date of Patent: August 6, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hiroshi Horikoshi, Minoru Ishida, Reijiroh Shohji, Tadashi Iijima, Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Masaki Haneda
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Patent number: 12046621Abstract: This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.Type: GrantFiled: March 15, 2022Date of Patent: July 23, 2024Assignee: SONY GROUP CORPORATIONInventors: Hajime Yamagishi, Kiyotaka Tabuchi, Masaki Okamoto, Takashi Oinoue, Minoru Ishida, Shota Hida, Kazutaka Yamane
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Patent number: 12027558Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line in another wiring layer.Type: GrantFiled: August 30, 2021Date of Patent: July 2, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
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Patent number: 12015161Abstract: The present invention relates to a catalyst for solid polymer fuel cells in which catalyst particles containing Pt as an essential catalyst metal are supported on a carbon powder carrier. The catalyst has good initial activity and good durability. When the catalyst is analyzed by X-ray photoelectron spectroscopy after potential holding at 1.2 V (vs. RHE) for 10 minutes in a perchloric acid solution, a ratio of zero-valent Pt to total Pt is 75% or more and 95% or less. The present inventive catalyst metal is preferably one obtained by alloying Pt with one of Co, Ni and Fe, and further with one of Mn, Ti, Zr and Sn. In addition, it is preferable that a fluorine compound having a C—F bond is supported on at least the surfaces of catalyst particles in an amount of 3 to 20 mass % based on the total mass of the catalyst.Type: GrantFiled: August 15, 2019Date of Patent: June 18, 2024Assignee: TANAKA KIKINZOKU KOGYO K.K.Inventor: Minoru Ishida
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Publication number: 20240194718Abstract: To provide a solid-state imaging device and an electronic apparatus with further improved performance. A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other.Type: ApplicationFiled: February 20, 2024Publication date: June 13, 2024Inventors: HIDETO HASHIGUCHI, REIJIROH SHOHJI, HIROSHI HORIKOSHI, IKUE MITSUHASHI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, MINORU ISHIDA, MASAKI HANEDA
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Patent number: 12002833Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.Type: GrantFiled: September 27, 2022Date of Patent: June 4, 2024Assignee: Sony Semiconductor Solutions CorporationInventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
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Patent number: 11990855Abstract: A drive system establishes a normal state in which a first switch is ON and a gang switch is OFF, in the case where it is determined that there is no abnormality in the state of a first rotating body driven by a first motor. In this normal state, the first motor is driven by a first inverter, while a second motor is driven by a second inverter. It the case where it is determined that there is abnormality in the state of the first rotating body, a first countermeasure state is established in which the first switch is OFF and the gang switch is ON. In this first countermeasure state, the second motor is driven by both the first inverter and the second inverter.Type: GrantFiled: March 29, 2022Date of Patent: May 21, 2024Assignee: DENSO CORPORATIONInventors: Minoru Ishida, Tsubasa Sakuishi, Yuki Takahashi
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Publication number: 20240147555Abstract: A communication system (100) includes: a plurality of stacked containers (2) having conductivity; and a plurality of electric field communication terminals (5) attached to the containers (2) in such a manner as to perform electric field coupling with any of the plurality of containers (2), in which the plurality of containers (2) includes a container (2) that contains a sensing terminal (4) that acquires sensing data, the plurality of electric field communication terminals (5) includes a first electric field communication terminal (5) attached to an inner side of the container (2) in which the sensing terminal (4) is contained, and a second electric field communication terminal (5) attached to an outer side of at least one container (2) of the plurality of containers (2), and the first electric field communication terminal (5) transmits the sensing data from the sensing terminal (4) to the second electric field communication terminal (5) via the plurality of containers (2).Type: ApplicationFiled: January 21, 2022Publication date: May 2, 2024Inventors: MOTOSUKE IRIE, KATSUKI HIRABAYASHI, YOSHINORI OOTA, KOICHI OSHIMA, MINORU ISHIDA
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Patent number: 11973091Abstract: The present disclosure relates to reducing the size of a solid-state imaging apparatus. The solid-state imaging apparatus is configured by laminating a first structure body, comprising a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned, and a second structure body, comprising an output circuit unit for outputting a pixel signal. The output circuit unit, including a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit.Type: GrantFiled: January 13, 2021Date of Patent: April 30, 2024Assignee: Sony CorporationInventors: Harumi Tanaka, Yoshiaki Masuda, Shinji Miyazawa, Minoru Ishida