Patents by Inventor Minoru Ishida

Minoru Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11411036
    Abstract: A solid-state imaging device includes a first substrate including a first semiconductor substrate and a first multi-layered wiring layer stacked on the first semiconductor substrate, a second substrate including a second semiconductor substrate and a second multi-layered wiring layer stacked on the second semiconductor substrate, a third substrate including a third semiconductor substrate and a third multi-layered wiring layer stacked on the third semiconductor substrate, and a first coupling structure for electrically coupling the first substrate and the second substrate. The first substrate, the second substrate, and the third substrate are stacked in this order. The first substrate and the second substrate are bonded together such that the first multi-layered wiring layer and the second multi-layered wiring layer are opposed to each other. The first substrate excludes a coupling structure formed from the first substrate as a base over bonding surfaces of the first substrate and the second substrate.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: August 9, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
  • Patent number: 11411037
    Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: August 9, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
  • Publication number: 20220224257
    Abstract: A drive system establishes a normal state in which a first switch is ON and a gang switch is OFF, in the case where it is determined that there is no abnormality in the state of a first rotating body driven by a first motor. In this normal state, the first motor is driven by a first inverter, while a second motor is driven by a second inverter. It the case where it is determined that there is abnormality in the state of the first rotating body, a first countermeasure state is established in which the first switch is OFF and the gang switch is ON. In this first countermeasure state, the second motor is driven by both the first inverter and the second inverter.
    Type: Application
    Filed: March 29, 2022
    Publication date: July 14, 2022
    Applicant: DENSO CORPORATION
    Inventors: Minoru ISHIDA, Tsubasa SAKUISHI, Yuki TAKAHASHI
  • Patent number: 11342371
    Abstract: A deformation of a stacked lens is suppressed. A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are bonded and stacked by direct bonding. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: May 24, 2022
    Assignee: SONY CORPORATION
    Inventors: Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Masanori Iwasaki, Toshihiko Hayashi, Shuzo Sato, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Minoru Ishida
  • Publication number: 20220157877
    Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.
    Type: Application
    Filed: February 3, 2022
    Publication date: May 19, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Reijiroh SHOHJI, Masaki HANEDA, Hiroshi HORIKOSHI, Minoru ISHIDA, Takatoshi KAMESHIMA, Ikue MITSUHASHI, Hideto HASHIGUCHI, Tadashi IIJIMA
  • Patent number: 11289525
    Abstract: This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: March 29, 2022
    Assignee: Sony Corporation
    Inventors: Hajime Yamagishi, Kiyotaka Tabuchi, Masaki Okamoto, Takashi Oinoue, Minoru Ishida, Shota Hida, Kazutaka Yamane
  • Patent number: 11289526
    Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: March 29, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Reijiroh Shohji, Masaki Haneda, Hiroshi Horikoshi, Minoru Ishida, Takatoshi Kameshima, Ikue Mitsuhashi, Hideto Hashiguchi, Tadashi Iijima
  • Publication number: 20220085093
    Abstract: To provide a solid-state imaging device and an electronic apparatus with further improved performance.
    Type: Application
    Filed: November 23, 2021
    Publication date: March 17, 2022
    Inventors: IKUE MITSUHASHI, REIJIROH SHOHJI, MINORU ISHIDA, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, HIROSHI HORIKOSHI, MASAKI HANEDA
  • Patent number: 11276866
    Abstract: The present invention relates to a catalyst for a solid polymer fuel cell that includes catalyst particles supported on a carbon powder carrier, the catalyst particles containing platinum, cobalt, and manganese. In the catalyst particles of the catalyst, the component ratio of platinum, cobalt, and manganese is Pt:Co:Mn=1:0.25 to 0.28:0.07 to 0.10 in a molar ratio, the average particle size is 3.4 to 5.0 nm, and further, in the particle size distribution of the catalyst particles, the proportion of catalyst particles having a particle size of 3.0 nm or less in the entire catalyst particles is 37% or less on a particle number basis. Then, a fluorine compound having a C—F bond is supported at least on the surface of the catalyst particles. The present invention is, with respect to the above ternary alloy catalyst, an invention particularly effective in improving the durability.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: March 15, 2022
    Assignee: TANAKA KIKINZOKU KOGYO K.K.
    Inventor: Minoru Ishida
  • Publication number: 20220043241
    Abstract: The present technology relates to, for example, a lens attached substrate including a substrate which has a through-hole formed therein and a light shielding film formed on a side wall of the through-hole and a lens resin portion which is formed inside the through-hole of the substrate. The present technology can be applied to, for example, a lens attached substrate, a layered lens structure, a camera module, a manufacturing apparatus, a manufacturing method, an electronic device, a computer, a program, a storage medium, a system, and the like.
    Type: Application
    Filed: October 26, 2021
    Publication date: February 10, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke MORIYA, Masanori IWASAKI, Takashi OINOUE, Yoshiya HAGIMOTO, Hiroyasu MATSUGAI, Hiroyuki ITOU, Suguru SAITO, Keiji OHSHIMA, Nobutoshi FUJII, Hiroshi TAZAWA, Toshiaki SHIRAIWA, Minoru ISHIDA
  • Publication number: 20210391372
    Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line in another wiring layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takatoshi KAMESHIMA, Hideto HASHIGUCHI, Ikue MITSUHASHI, Hiroshi HORIKOSHI, Reijiroh SHOHJI, Minoru ISHIDA, Tadashi IIJIMA, Masaki HANEDA
  • Patent number: 11201185
    Abstract: Provided is a solid-state imaging device including a first substrate that includes a pixel unit, a first semiconductor substrate, and a first multi-layered wiring layer stacked, a second substrate that includes circuit, a second semiconductor substrate, and a second multi-layered wiring layer stacked, the circuit having a predetermined function, a third substrate that includes a circuit, a third semiconductor substrate, and a third multi-layered wiring layer. The first substrate and the second substrate being bonded together such that the first multi-layered wiring layer is opposite to the second semiconductor substrate, and a first coupling structure for electrically coupling the circuit of the first substrate with the circuit of the second substrate, the first coupling structure is on bonding surfaces of the first substrate and the second substrate, and includes an electrode junction structure in which electrodes on the respective bonding surfaces are joined to each other in direct contact.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: December 14, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Ikue Mitsuhashi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Takatoshi Kameshima, Hideto Hashiguchi, Hiroshi Horikoshi, Masaki Haneda
  • Patent number: 11194135
    Abstract: The present technology relates to, for example, a lens attached substrate including a substrate which has a through-hole formed therein and a light shielding film formed on a side wall of the through-hole and a lens resin portion which is formed inside the through-hole of the substrate. The present technology can be applied to, for example, a lens attached substrate, a layered lens structure, a camera module, a manufacturing apparatus, a manufacturing method, an electronic device, a computer, a program, a storage medium, a system, and the like.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: December 7, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yusuke Moriya, Masanori Iwasaki, Takashi Oinoue, Yoshiya Hagimoto, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Minoru Ishida
  • Publication number: 20210366973
    Abstract: Provided are a solid-state imaging device and an electronic apparatus with further improved performance. The solid-state imaging device including a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked, a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked, and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together with the first multi-layered wiring layer and the second semiconductor substrate opposed to each other.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Inventors: HIROSHI HORIKOSHI, MINORU ISHIDA, REIJIROH SHOHJI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, IKUE MITSUHASHI, MASAKI HANEDA
  • Patent number: 11156196
    Abstract: A starting device is used in a starting system that includes a starting electric motor unit and a rotating electrical machine; the starting electric motor unit including a motor that rotates a pinion gear, and a pushing member that pushes out the pinion gear toward a ring gear, the ring gear rotating together with a crankshaft of an engine; the rotating electrical machine being connected to the crankshaft and rotating the crankshaft; the starting system being configured to push, using the pushing member, the pinion gear toward the ring gear, and drive the motor to rotate, based on driving force of the motor, the ring gear via the pinion gear, thus starting the engine. The starting device includes a drive instruction unit that instructs the rotating electrical machine to rotate the ring gear via the crankshaft during a pre-drive period before drive of the motor.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: October 26, 2021
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Minoru Ishida, Minoru Okamiya, Takayuki Kogure, Hiroshi Enomoto, Takahisa Miura
  • Publication number: 20210328230
    Abstract: The present invention relates to a catalyst for solid polymer fuel cells in which catalyst particles containing Pt as an essential catalyst metal are supported on a carbon powder carrier. The catalyst has good initial activity and good durability. When the catalyst is analyzed by X-ray photoelectron spectroscopy after potential holding at 1.2 V (vs. RHE) for 10 minutes in a perchloric acid solution, a ratio of zero-valent Pt to total Pt is 75% or more and 95% or less. The present inventive catalyst metal is preferably one obtained by alloying Pt with one of Co, Ni and Fe, and further with one of Mn, Ti, Zr and Sn. In addition, it is preferable that a fluorine compound having a C—F bond is supported on at least the surfaces of catalyst particles in an amount of 3 to 20 mass % based on the total mass of the catalyst.
    Type: Application
    Filed: August 15, 2019
    Publication date: October 21, 2021
    Applicant: TANAKA KIKINZOKU KOGYO K.K.
    Inventor: Minoru ISHIDA
  • Patent number: 11152418
    Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line in another wiring layer.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: October 19, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
  • Publication number: 20210313375
    Abstract: The present disclosure relates to a semiconductor device, a solid-state image pickup element, an image pickup device, and an electronic apparatus that are enabled to reduce restrictions on materials and restrictions on device configuration. A CSP imager and a mounting substrate are connected together with a connection portion other than a solder ball. With such a configuration, restrictions on materials and restrictions on device configuration are reduced, which has conventionally occurred because it is limited to a configuration in which solder balls are used for connection. The present disclosure can be applied to image pickup devices.
    Type: Application
    Filed: May 13, 2021
    Publication date: October 7, 2021
    Applicant: SONY GROUP CORPORATION
    Inventors: Yoshiaki MASUDA, Minoru ISHIDA
  • Patent number: 11130299
    Abstract: To suppress occurrence of contamination or damage to a lens. In the present technology, for example, a manufacturing apparatus allows a spacer which is thicker than a height of a lens resin portion protruded from a substrate to be adhered to the substrate. In addition, for example, in the present technology, the manufacturing apparatus molds the lens resin portion inside a through-hole formed in the substrate by using a mold frame configured with two layers of molds and, after molding the lens resin portion, in the state that one mold is adhered to the substrate, the manufacturing apparatus demolds the substrate from the other mold. The present technology can be applied to, for example, a lens-attached substrate, a stacked lens structure, a camera module, a manufacturing apparatus, a manufacturing method, an electronic apparatus, a computer, a program, a storage medium, a system, or the like.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: September 28, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hiroshi Tazawa, Toshihiro Kurobe, Sotetsu Saito, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Nobutoshi Fujii, Toshiaki Shiraiwa, Minoru Ishida
  • Patent number: 11101313
    Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together with the first multi-layered wiring layer and the second semiconductor substrate opposed to each other.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: August 24, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroshi Horikoshi, Minoru Ishida, Reijiroh Shohji, Tadashi Iijima, Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Masaki Haneda