Patents by Inventor Minoru Ishida
Minoru Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11543621Abstract: There is provided a camera module including a stacked lens structure including a plurality of lens substrates. The plurality of lens substrates includes a first lens substrate including a first lens that is disposed at an inner side of a through-hole formed in the first lens substrate, and a second lens substrate including a second lens that is disposed at an inner side of a through-hole formed in the second lens substrate, wherein the first lens substrate is directly bonded to the second lens substrate. The camera module further includes an electromagnetic drive unit configured to adjust a distance between the stacked lens structure and a light-receiving element.Type: GrantFiled: January 16, 2018Date of Patent: January 3, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Munekatsu Fukuyama, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Masanori Iwasaki, Toshihiko Hayashi, Shuzo Sato, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Yusuke Moriya, Minoru Ishida
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Patent number: 11525984Abstract: The present technology relates to, for example, a lens attached substrate including a substrate which has a through-hole formed therein and a light shielding film formed on a side wall of the through-hole and a lens resin portion which is formed inside the through-hole of the substrate. The present technology can be applied to, for example, a lens attached substrate, a layered lens structure, a camera module, a manufacturing apparatus, a manufacturing method, an electronic device, a computer, a program, a storage medium, a system, and the like.Type: GrantFiled: October 26, 2021Date of Patent: December 13, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Yusuke Moriya, Masanori Iwasaki, Takashi Oinoue, Yoshiya Hagimoto, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Minoru Ishida
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Patent number: 11527568Abstract: Provided are a first photoelectric conversion unit, a second photoelectric conversion unit having a smaller electric charge amount to be converted per unit time than the first photoelectric conversion unit, a charge accumulation unit that accumulates an electric charge generated by the second photoelectric conversion unit, a charge voltage conversion unit, a first transfer gate unit that transfers an electric charge from the first photoelectric conversion unit to the charge voltage conversion unit, a second transfer gate unit that couples potentials of the charge voltage conversion unit and the charge accumulation unit, a third transfer gate unit that transfers an electric charge from the second photoelectric conversion unit to the charge accumulation unit, an overflow path formed under a gate electrode of the third transfer gate unit and transfers an electric charge overflowing from the second photoelectric conversion unit to the charge accumulation unit, and a light reducing unit that reduces light to enterType: GrantFiled: February 24, 2017Date of Patent: December 13, 2022Assignee: SONY CORPORATIONInventors: Tomohiko Asatsuma, Minoru Ishida
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Publication number: 20220359603Abstract: A solid-state imaging device is provided that comprises a first substrate that includes a first multi-layered wiring layer stacked on a first semiconductor substrate, a second substrate that includes a second multi-layered wiring layer and an insulating layer stacked on a second semiconductor substrate, and a third substrate that includes a third multi-layered wiring layer stacked on a third semiconductor substrate. A first coupling structure electrically couples the first and second substrates to each other. A second coupling structure exists on bonding surfaces of the second and third substrates, and includes an electrode junction structure in which electrodes formed on respective bonding surfaces are in direct contact with each other. A first via penetrates the second semiconductor substrate and electrically couples a first electrode to a wiring in the second multi-layered wiring layer. A second via electrically couples the second electrode to another wiring in the third multi-layered wiring layer.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, IKUE MITSUHASHI, HIROSHI HORIKOSHI, REIJIROH SHOHJI, MINORU ISHIDA, TADASHI IIJIMA, MASAKI HANEDA
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Publication number: 20220359605Abstract: To provide a solid-state imaging device and an electronic apparatus with further improved performance. A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: HIDETO HASHIGUCHI, REIJIROH SHOHJI, HIROSHI HORIKOSHI, IKUE MITSUHASHI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, MINORU ISHIDA, MASAKI HANEDA
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Publication number: 20220348077Abstract: A drive control device is applicable to a vehicle including a first motor which drives a first wheel and a second motor which drives a second wheel. The drive control device includes a sensor, a torque setting section, an anomaly detection section, and an information output section. The sensor detects information about the drive control device. The torque setting section sets upper limit values of torques that can be generated by the first motor and the second motor based on the information detected by the sensor. The anomaly detection section detects an anomaly in the drive control device. In response to the anomaly detection section detecting the anomaly, the information output section outputs, to the torque setting section, setting information that sets the upper limit values of the torques of the first motor and the second motor to a common predetermined value, as the information.Type: ApplicationFiled: July 13, 2022Publication date: November 3, 2022Applicant: DENSO CORPORATIONInventors: Minoru ISHIDA, Harumi HORIHATA
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Patent number: 11476294Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.Type: GrantFiled: March 29, 2021Date of Patent: October 18, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
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Patent number: 11456643Abstract: A rotating electric machine includes a rotor rotatably supported and also including a magnet portion; a stator including a stator winding; and a plunger configured to displace the rotor and the stator relative to one another along an axial direction of the rotating electric machine. The stator includes a slotless structure in which at least one of no magnetic teeth and slot is provided. Thus, an attracting force acting between the magnet portion and the stator is weakened, thereby the rotor and the stator are easily displaceable relative to each other by the plunger.Type: GrantFiled: October 1, 2019Date of Patent: September 27, 2022Assignee: DENSO CORPORATIONInventors: Minoru Ishida, Naoki Katayama, Tsubasa Sakuishi, Yuki Takahashi
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Publication number: 20220278160Abstract: This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.Type: ApplicationFiled: March 15, 2022Publication date: September 1, 2022Inventors: HAJIME YAMAGISHI, KIYOTAKA TABUCHI, MASAKI OKAMOTO, TAKASHI OINOUE, MINORU ISHIDA, SHOTA HIDA, KAZUTAKA YAMANE
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Patent number: 11411036Abstract: A solid-state imaging device includes a first substrate including a first semiconductor substrate and a first multi-layered wiring layer stacked on the first semiconductor substrate, a second substrate including a second semiconductor substrate and a second multi-layered wiring layer stacked on the second semiconductor substrate, a third substrate including a third semiconductor substrate and a third multi-layered wiring layer stacked on the third semiconductor substrate, and a first coupling structure for electrically coupling the first substrate and the second substrate. The first substrate, the second substrate, and the third substrate are stacked in this order. The first substrate and the second substrate are bonded together such that the first multi-layered wiring layer and the second multi-layered wiring layer are opposed to each other. The first substrate excludes a coupling structure formed from the first substrate as a base over bonding surfaces of the first substrate and the second substrate.Type: GrantFiled: March 23, 2018Date of Patent: August 9, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
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Patent number: 11411037Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other.Type: GrantFiled: March 23, 2018Date of Patent: August 9, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
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Publication number: 20220224257Abstract: A drive system establishes a normal state in which a first switch is ON and a gang switch is OFF, in the case where it is determined that there is no abnormality in the state of a first rotating body driven by a first motor. In this normal state, the first motor is driven by a first inverter, while a second motor is driven by a second inverter. It the case where it is determined that there is abnormality in the state of the first rotating body, a first countermeasure state is established in which the first switch is OFF and the gang switch is ON. In this first countermeasure state, the second motor is driven by both the first inverter and the second inverter.Type: ApplicationFiled: March 29, 2022Publication date: July 14, 2022Applicant: DENSO CORPORATIONInventors: Minoru ISHIDA, Tsubasa SAKUISHI, Yuki TAKAHASHI
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Patent number: 11342371Abstract: A deformation of a stacked lens is suppressed. A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are bonded and stacked by direct bonding. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.Type: GrantFiled: July 31, 2020Date of Patent: May 24, 2022Assignee: SONY CORPORATIONInventors: Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Masanori Iwasaki, Toshihiko Hayashi, Shuzo Sato, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Minoru Ishida
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Publication number: 20220157877Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.Type: ApplicationFiled: February 3, 2022Publication date: May 19, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Reijiroh SHOHJI, Masaki HANEDA, Hiroshi HORIKOSHI, Minoru ISHIDA, Takatoshi KAMESHIMA, Ikue MITSUHASHI, Hideto HASHIGUCHI, Tadashi IIJIMA
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Patent number: 11289525Abstract: This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.Type: GrantFiled: March 11, 2016Date of Patent: March 29, 2022Assignee: Sony CorporationInventors: Hajime Yamagishi, Kiyotaka Tabuchi, Masaki Okamoto, Takashi Oinoue, Minoru Ishida, Shota Hida, Kazutaka Yamane
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Patent number: 11289526Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.Type: GrantFiled: March 23, 2018Date of Patent: March 29, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Reijiroh Shohji, Masaki Haneda, Hiroshi Horikoshi, Minoru Ishida, Takatoshi Kameshima, Ikue Mitsuhashi, Hideto Hashiguchi, Tadashi Iijima
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Publication number: 20220085093Abstract: To provide a solid-state imaging device and an electronic apparatus with further improved performance.Type: ApplicationFiled: November 23, 2021Publication date: March 17, 2022Inventors: IKUE MITSUHASHI, REIJIROH SHOHJI, MINORU ISHIDA, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, HIROSHI HORIKOSHI, MASAKI HANEDA
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Patent number: 11276866Abstract: The present invention relates to a catalyst for a solid polymer fuel cell that includes catalyst particles supported on a carbon powder carrier, the catalyst particles containing platinum, cobalt, and manganese. In the catalyst particles of the catalyst, the component ratio of platinum, cobalt, and manganese is Pt:Co:Mn=1:0.25 to 0.28:0.07 to 0.10 in a molar ratio, the average particle size is 3.4 to 5.0 nm, and further, in the particle size distribution of the catalyst particles, the proportion of catalyst particles having a particle size of 3.0 nm or less in the entire catalyst particles is 37% or less on a particle number basis. Then, a fluorine compound having a C—F bond is supported at least on the surface of the catalyst particles. The present invention is, with respect to the above ternary alloy catalyst, an invention particularly effective in improving the durability.Type: GrantFiled: September 20, 2018Date of Patent: March 15, 2022Assignee: TANAKA KIKINZOKU KOGYO K.K.Inventor: Minoru Ishida
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Publication number: 20220043241Abstract: The present technology relates to, for example, a lens attached substrate including a substrate which has a through-hole formed therein and a light shielding film formed on a side wall of the through-hole and a lens resin portion which is formed inside the through-hole of the substrate. The present technology can be applied to, for example, a lens attached substrate, a layered lens structure, a camera module, a manufacturing apparatus, a manufacturing method, an electronic device, a computer, a program, a storage medium, a system, and the like.Type: ApplicationFiled: October 26, 2021Publication date: February 10, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yusuke MORIYA, Masanori IWASAKI, Takashi OINOUE, Yoshiya HAGIMOTO, Hiroyasu MATSUGAI, Hiroyuki ITOU, Suguru SAITO, Keiji OHSHIMA, Nobutoshi FUJII, Hiroshi TAZAWA, Toshiaki SHIRAIWA, Minoru ISHIDA
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Publication number: 20210391372Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line in another wiring layer.Type: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takatoshi KAMESHIMA, Hideto HASHIGUCHI, Ikue MITSUHASHI, Hiroshi HORIKOSHI, Reijiroh SHOHJI, Minoru ISHIDA, Tadashi IIJIMA, Masaki HANEDA