Abstract: Provided is an output circuit including a logic circuit, a capacitor, a buffer circuit, and a driver circuit. When a clock signal is input and an enable signal is active, the logic circuit outputs a clock signal based on the clock signal. The buffer circuit receives a signal that is an output signal of the logic circuit via the capacitor. The driver circuit outputs a clock signal based on a signal that is an output signal of the buffer circuit. The logic circuit sets a signal to the same logic level as an input node of the buffer circuit when the enable signal is inactive.

Abstract: A circuit device includes first and second output signal lines from which first and second output signals constituting differential output signals are output, and first to n-th output drivers coupled to the first and second output signal lines. In a first mode, i number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on first and second input signals constituting differential input signals. In a second mode, j number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on the first and second input signals.

Abstract: Provided is an output circuit including a logic circuit, a capacitor, a buffer circuit, and a driver circuit. When a clock signal is input and an enable signal is active, the logic circuit outputs a clock signal based on the clock signal. The buffer circuit receives a signal that is an output signal of the logic circuit via the capacitor. The driver circuit outputs a clock signal based on a signal that is an output signal of the buffer circuit. The logic circuit sets a signal to the same logic level as an input node of the buffer circuit when the enable signal is inactive.

Abstract: An output circuit includes first and second nodes, a regulator, a pre-driver, and an output driver. The regulator outputs a second voltage to the second node based on a first voltage applied to the first node. The output driver receives a signal from the pre-driver and outputs a second signal. The regulator short-circuits the first and second nodes while the pre-driver is in a standby state, and controls the second voltage to be different from the first voltage after the pre-driver transitions from the standby state to a normal operation state.

Abstract: A circuit device includes first and second output signal lines from which first and second output signals constituting differential output signals are output, and first to n-th output drivers coupled to the first and second output signal lines. In a first mode, i number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on first and second input signals constituting differential input signals. In a second mode, j number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on the first and second input signals.

Abstract: An output circuit includes: a first node to which a first voltage is applied; a second node to which a second voltage is applied; a regulator which outputs the second voltage to the second node based on the first voltage applied to the first node; a pre-driver to which a first signal is input and which operates based on the second voltage; and an output driver to which a signal from the pre-driver is input and which outputs a second signal. The regulator short-circuits the first node and the second node while the pre-driver is in a standby state, and controls the second voltage to be different from the first voltage after the pre-driver transitions from the standby state to a normal operation state.

Abstract: In order to achieve a circuit device capable of stably supplying an antenna with electric power in a broad power range to output a transmission signal, the circuit device includes a current source adapted to supply a first current in a first operation mode, and supply a second current higher than the first current in a second operation mode, and a drive section supplied with the electric power from the current source, and adapted to perform drive for outputting a transmission signal to an antenna via a matching circuit.

Abstract: In order to achieve a circuit device capable of stably supplying an antenna with electric power in a broad power range to output a transmission signal, the circuit device includes a current source adapted to supply a first current in a first operation mode, and supply a second current higher than the first current in a second operation mode, and a drive section supplied with the electric power from the current source, and adapted to perform drive for outputting a transmission signal to an antenna via a matching circuit.

Abstract: An output circuit includes a first circuit that generates a first output voltage based on a resistance ratio, on the basis of a reference voltage, a second circuit that compares the first output voltage with a source voltage of a second transistor that sets a second output voltage of the output signal, and generates an output gate voltage for causing the first transistor to output the second output voltage, and a third circuit that controls a timing at which the output gate voltage is applied to the first transistor, on the basis of an input control signal.

Abstract: An output circuit includes a first circuit that generates a first output voltage based on a resistance ratio, on the basis of a reference voltage, a second circuit that compares the first output voltage with a source voltage of a second transistor that sets a second output voltage of the output signal, and generates an output gate voltage for causing the first transistor to output the second output voltage, and a third circuit that controls a timing at which the output gate voltage is applied to the first transistor, on the basis of an input control signal.

Abstract: A DC-DC converter is provided. The DC-DC converter is connected to a PLL circuit, supplying a voltage at least to a power source terminal of a voltage controlled oscillator of the PLL circuit. A frequency of a ripple voltage included in the voltage is less than a natural frequency of the PLL circuit or more than one-half of a frequency of an output signal of the PLL circuit.

Abstract: A circuit is provided to prevent improper locking of a DLL circuit without providing any limitation to the reference clock frequency. By detecting the time difference between edges of multi-phase clocks Ck1–Ck6, a delay time detection signal DT1 corresponding to a delay time 5? from the multi-phase clock Ck1 to the multi-phase clock Ck6 is generated. An Up1 signal is forcibly output to a charge pump circuit CP1 based on this delay time detection signal DT1, and the output of a Down1 signal is suppressed.

Abstract: In a circuit block BL1, a PMOS transistor P1 and a PMOS transistor P1? are connected in series between a high-level potential HL and an output terminal U1; an NMOS transistor N1 and an NMOS transistor N1? are connected in series between a low-level potential LL and the output terminal U1. An inversion signal Ck1B of a clock signal Ck1 is inputted to the gate of the PMOS transistor P1; the inversion signal Ck1B of the clock signal Ck1 is inputted to the gate of the PMOS transistor P1? through an inverter IV1; a clock signal Ck2 is inputted to the gate of the NMOS transistor N1; and the clock signal Ck2 is inputted to the gate of the NMOS transister N1? through an inverter IV2.

Abstract: A DC-DC converter is provided. The DC-DC converter is connected to a PLL circuit, supplying a voltage at least to a power source terminal of a voltage controlled oscillator of the PLL circuit. A frequency of a ripple voltage included in the voltage is less than a natural frequency of the PLL circuit or more than one-half of a frequency of an output signal of the PLL circuit.

Abstract: PMOS transistors P1-Pn and PMOS transistors P1?-Pn? are respectively connected in series between a supply voltage terminal VD and output terminals OUTB, while NMOS transistors N1-Nn and NMOS transistors N1?-Nn? are respectively connected in series between the output terminals OUTB and a ground terminal G. Input terminals S1-Sn are respectively connected to the gates of the PMOS transistors P1?-Pn? and NMOS transistors N1-Nn, and they are respectively connected to the gates of the PMOS transistors P1-Pn and NMOS transistors N1?-Nn? through corresponding inverters IV1-IVn.

Abstract: A circuit is provided to make the propagation delay time of each signal path substantially the same without using a low resistance process even when wiring lengths are different. In the circuit, output nodes a to d are individually disposed at the output side of transmission gates TG2, TG4, TG6, and TG8, these output nodes a to d are connected so as to have an equal wiring length, inverters IV11 and IV12 are disposed at the output nodes a and d, and a common node e is disposed at a position where the wiring length from each of the inverters IV11 and IV12 becomes identical.

Abstract: A circuit is provided to make the propagation delay time of each signal path substantially the same without using a low resistance process even when wiring lengths are different. In the circuit, output nodes a to d are individually disposed at the output side of transmission gates TG2, TG4, TG6, and TG8, these output nodes a to d are connected so as to have an equal wiring length, inverters IV11 and IV12 are disposed at the output nodes a and d, and a common node e is disposed at a position where the wiring length from each of the inverters IV11 and IV12 becomes identical.

Abstract: The ring oscillator circuit is made by connecting K units of inverter circuits U11, U12, . . . , U1K in a ring shape. The inverter circuit U11 comprises a CMOS inverter IV1 which includes MOS transistors MP4 and MN4, a P-channel MOS transistor MP3 which functions as the current source for a CMOS inverter IV1, an N-channel MOS transistor MN3 which functions as the current source for a CMOS inverter IV1, and a CMOS inverter IV2 which is connected in parallel to the CMOS inverter IV1 and includes MOS transistors MP5 and MN5.

Abstract: A circuit is provided to prevent improper locking of a DLL circuit without providing any limitation to the reference clock frequency. By detecting the time difference between edges of multi-phase clocks Ck1-Ck6, a delay time detection signal DT1 corresponding to a delay time 5&tgr; from the multi-phase clock Ck1 to the multi-phase clock Ck6 is generated. An Up1 signal is forcibly output to a charge pump circuit CP1 based on this delay time detection signal DT1, and the output of a Down1 signal is suppressed.

Abstract: In a circuit block BL1, a PMOS transistor P1 and a PMOS transistor P1′ are connected in a series between a high-level potential HL and an output terminal U1; an NMOS transister N1 and an NMOS transistor N1′ are connected in series between a low-level potential LL and the output terminal U1. An inversion signal Ck1B of a clock signal Ck1 is inputted to the gate of the PMOS transistor P1; the inversion signal Ck1B of the clock signal Ck1 is inputted to the gate of the PMOS transistor P1′ through an inverter IV1; a clock signal Ck2 is inputted to the gate of the NMOS transistor N1; and the clock signal Ck2 is inputted to the gate of the NMOS transister N1′ through an inverter IV2.