Patents by Inventor Minoru Kozaki

Minoru Kozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10797705
    Abstract: A circuit device includes first and second output signal lines from which first and second output signals constituting differential output signals are output, and first to n-th output drivers coupled to the first and second output signal lines. In a first mode, i number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on first and second input signals constituting differential input signals. In a second mode, j number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on the first and second input signals.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: October 6, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Fumikazu Komatsu, Minoru Kozaki
  • Publication number: 20200313658
    Abstract: Provided is an output circuit including a logic circuit, a capacitor, a buffer circuit, and a driver circuit. When a clock signal is input and an enable signal is active, the logic circuit outputs a clock signal based on the clock signal. The buffer circuit receives a signal that is an output signal of the logic circuit via the capacitor. The driver circuit outputs a clock signal based on a signal that is an output signal of the buffer circuit. The logic circuit sets a signal to the same logic level as an input node of the buffer circuit when the enable signal is inactive.
    Type: Application
    Filed: March 27, 2020
    Publication date: October 1, 2020
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Minoru KOZAKI
  • Patent number: 10742168
    Abstract: An output circuit includes first and second nodes, a regulator, a pre-driver, and an output driver. The regulator outputs a second voltage to the second node based on a first voltage applied to the first node. The output driver receives a signal from the pre-driver and outputs a second signal. The regulator short-circuits the first and second nodes while the pre-driver is in a standby state, and controls the second voltage to be different from the first voltage after the pre-driver transitions from the standby state to a normal operation state.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: August 11, 2020
    Assignee: Seiko Epson Corporation
    Inventor: Minoru Kozaki
  • Publication number: 20200083844
    Abstract: A circuit device includes first and second output signal lines from which first and second output signals constituting differential output signals are output, and first to n-th output drivers coupled to the first and second output signal lines. In a first mode, i number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on first and second input signals constituting differential input signals. In a second mode, j number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on the first and second input signals.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 12, 2020
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Fumikazu KOMATSU, Minoru KOZAKI
  • Publication number: 20190267942
    Abstract: An output circuit includes: a first node to which a first voltage is applied; a second node to which a second voltage is applied; a regulator which outputs the second voltage to the second node based on the first voltage applied to the first node; a pre-driver to which a first signal is input and which operates based on the second voltage; and an output driver to which a signal from the pre-driver is input and which outputs a second signal. The regulator short-circuits the first node and the second node while the pre-driver is in a standby state, and controls the second voltage to be different from the first voltage after the pre-driver transitions from the standby state to a normal operation state.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 29, 2019
    Inventor: Minoru KOZAKI
  • Patent number: 9564875
    Abstract: In order to achieve a circuit device capable of stably supplying an antenna with electric power in a broad power range to output a transmission signal, the circuit device includes a current source adapted to supply a first current in a first operation mode, and supply a second current higher than the first current in a second operation mode, and a drive section supplied with the electric power from the current source, and adapted to perform drive for outputting a transmission signal to an antenna via a matching circuit.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: February 7, 2017
    Assignee: Seiko Epson Corporation
    Inventors: Minoru Kozaki, Shoichiro Kasahara
  • Publication number: 20160020751
    Abstract: In order to achieve a circuit device capable of stably supplying an antenna with electric power in a broad power range to output a transmission signal, the circuit device includes a current source adapted to supply a first current in a first operation mode, and supply a second current higher than the first current in a second operation mode, and a drive section supplied with the electric power from the current source, and adapted to perform drive for outputting a transmission signal to an antenna via a matching circuit.
    Type: Application
    Filed: July 14, 2015
    Publication date: January 21, 2016
    Inventors: Minoru KOZAKI, Shoichiro KASAHARA
  • Patent number: 9100005
    Abstract: An output circuit includes a first circuit that generates a first output voltage based on a resistance ratio, on the basis of a reference voltage, a second circuit that compares the first output voltage with a source voltage of a second transistor that sets a second output voltage of the output signal, and generates an output gate voltage for causing the first transistor to output the second output voltage, and a third circuit that controls a timing at which the output gate voltage is applied to the first transistor, on the basis of an input control signal.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: August 4, 2015
    Assignee: Seiko Epson Corporation
    Inventor: Minoru Kozaki
  • Publication number: 20140292425
    Abstract: An output circuit includes a first circuit that generates a first output voltage based on a resistance ratio, on the basis of a reference voltage, a second circuit that compares the first output voltage with a source voltage of a second transistor that sets a second output voltage of the output signal, and generates an output gate voltage for causing the first transistor to output the second output voltage, and a third circuit that controls a timing at which the output gate voltage is applied to the first transistor, on the basis of an input control signal.
    Type: Application
    Filed: March 19, 2014
    Publication date: October 2, 2014
    Applicant: Seiko Epson Corporation
    Inventor: Minoru Kozaki
  • Patent number: 7199627
    Abstract: A DC-DC converter is provided. The DC-DC converter is connected to a PLL circuit, supplying a voltage at least to a power source terminal of a voltage controlled oscillator of the PLL circuit. A frequency of a ripple voltage included in the voltage is less than a natural frequency of the PLL circuit or more than one-half of a frequency of an output signal of the PLL circuit.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: April 3, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Minoru Kozaki
  • Patent number: 7073098
    Abstract: A circuit is provided to prevent improper locking of a DLL circuit without providing any limitation to the reference clock frequency. By detecting the time difference between edges of multi-phase clocks Ck1–Ck6, a delay time detection signal DT1 corresponding to a delay time 5? from the multi-phase clock Ck1 to the multi-phase clock Ck6 is generated. An Up1 signal is forcibly output to a charge pump circuit CP1 based on this delay time detection signal DT1, and the output of a Down1 signal is suppressed.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: July 4, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Minoru Kozaki
  • Patent number: 6967512
    Abstract: In a circuit block BL1, a PMOS transistor P1 and a PMOS transistor P1? are connected in series between a high-level potential HL and an output terminal U1; an NMOS transistor N1 and an NMOS transistor N1? are connected in series between a low-level potential LL and the output terminal U1. An inversion signal Ck1B of a clock signal Ck1 is inputted to the gate of the PMOS transistor P1; the inversion signal Ck1B of the clock signal Ck1 is inputted to the gate of the PMOS transistor P1? through an inverter IV1; a clock signal Ck2 is inputted to the gate of the NMOS transistor N1; and the clock signal Ck2 is inputted to the gate of the NMOS transister N1? through an inverter IV2.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: November 22, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Minoru Kozaki
  • Publication number: 20050127887
    Abstract: A DC-DC converter is provided. The DC-DC converter is connected to a PLL circuit, supplying a voltage at least to a power source terminal of a voltage controlled oscillator of the PLL circuit. A frequency of a ripple voltage included in the voltage is less than a natural frequency of the PLL circuit or more than one-half of a frequency of an output signal of the PLL circuit.
    Type: Application
    Filed: December 14, 2004
    Publication date: June 16, 2005
    Inventor: Minoru Kozaki
  • Patent number: 6900684
    Abstract: PMOS transistors P1-Pn and PMOS transistors P1?-Pn? are respectively connected in series between a supply voltage terminal VD and output terminals OUTB, while NMOS transistors N1-Nn and NMOS transistors N1?-Nn? are respectively connected in series between the output terminals OUTB and a ground terminal G. Input terminals S1-Sn are respectively connected to the gates of the PMOS transistors P1?-Pn? and NMOS transistors N1-Nn, and they are respectively connected to the gates of the PMOS transistors P1-Pn and NMOS transistors N1?-Nn? through corresponding inverters IV1-IVn.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: May 31, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Minoru Kozaki
  • Patent number: 6882211
    Abstract: A circuit is provided to make the propagation delay time of each signal path substantially the same without using a low resistance process even when wiring lengths are different. In the circuit, output nodes a to d are individually disposed at the output side of transmission gates TG2, TG4, TG6, and TG8, these output nodes a to d are connected so as to have an equal wiring length, inverters IV11 and IV12 are disposed at the output nodes a and d, and a common node e is disposed at a position where the wiring length from each of the inverters IV11 and IV12 becomes identical.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: April 19, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Minoru Kozaki
  • Publication number: 20040008073
    Abstract: A circuit is provided to make the propagation delay time of each signal path substantially the same without using a low resistance process even when wiring lengths are different. In the circuit, output nodes a to d are individually disposed at the output side of transmission gates TG2, TG4, TG6, and TG8, these output nodes a to d are connected so as to have an equal wiring length, inverters IV11 and IV12 are disposed at the output nodes a and d, and a common node e is disposed at a position where the wiring length from each of the inverters IV11 and IV12 becomes identical.
    Type: Application
    Filed: February 5, 2003
    Publication date: January 15, 2004
    Inventor: Minoru Kozaki
  • Patent number: 6677825
    Abstract: The ring oscillator circuit is made by connecting K units of inverter circuits U11, U12, . . . , U1K in a ring shape. The inverter circuit U11 comprises a CMOS inverter IV1 which includes MOS transistors MP4 and MN4, a P-channel MOS transistor MP3 which functions as the current source for a CMOS inverter IV1, an N-channel MOS transistor MN3 which functions as the current source for a CMOS inverter IV1, and a CMOS inverter IV2 which is connected in parallel to the CMOS inverter IV1 and includes MOS transistors MP5 and MN5.
    Type: Grant
    Filed: May 20, 2002
    Date of Patent: January 13, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Minoru Kozaki
  • Publication number: 20030188235
    Abstract: A circuit is provided to prevent improper locking of a DLL circuit without providing any limitation to the reference clock frequency. By detecting the time difference between edges of multi-phase clocks Ck1-Ck6, a delay time detection signal DT1 corresponding to a delay time 5&tgr; from the multi-phase clock Ck1 to the multi-phase clock Ck6 is generated. An Up1 signal is forcibly output to a charge pump circuit CP1 based on this delay time detection signal DT1, and the output of a Down1 signal is suppressed.
    Type: Application
    Filed: February 14, 2003
    Publication date: October 2, 2003
    Inventor: Minoru Kozaki
  • Publication number: 20030137333
    Abstract: In a circuit block BL1, a PMOS transistor P1 and a PMOS transistor P1′ are connected in a series between a high-level potential HL and an output terminal U1; an NMOS transister N1 and an NMOS transistor N1′ are connected in series between a low-level potential LL and the output terminal U1. An inversion signal Ck1B of a clock signal Ck1 is inputted to the gate of the PMOS transistor P1; the inversion signal Ck1B of the clock signal Ck1 is inputted to the gate of the PMOS transistor P1′ through an inverter IV1; a clock signal Ck2 is inputted to the gate of the NMOS transistor N1; and the clock signal Ck2 is inputted to the gate of the NMOS transister N1′ through an inverter IV2.
    Type: Application
    Filed: December 26, 2002
    Publication date: July 24, 2003
    Inventor: Minoru Kozaki
  • Publication number: 20030080783
    Abstract: PMOS transistors P1-Pn and PMOS transistors P1′-Pn′ are respectively connected in series between a supply voltage terminal VD and output terminals OUTB, while NMOS transistors N1-Nn and NMOS transistors N1′-Nn′ are respectively connected in series between the output terminals OUTB and a ground terminal G. Input terminals S1-Sn are respectively connected to the gates of the PMOS transistors P1′-Pn′ and NMOS transistors N1-Nn, and they are respectively connected to the gates of the PMOS transistors P1-Pn and NMOS transistors N1′-Nn′ through corresponding inverters IV1-IVn.
    Type: Application
    Filed: October 15, 2002
    Publication date: May 1, 2003
    Inventor: Minoru Kozaki