Patents by Inventor Minoru Okamoto

Minoru Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10465759
    Abstract: A piston has a piston main body including an aluminum alloy, and a covering layer formed on the outer surface of the piston main body, and the covering layer has a first plating layer including an iron-phosphorous alloy, and a second plating layer including a nickel-phosphorous alloy formed on the first plating layer.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: November 5, 2019
    Assignees: NISSIN KOGYO CO., LTD., SHINSHU UNIVERSITY
    Inventors: Minoru Okamoto, Yohei Takahashi, Susumu Arai, Miyoka Ueda
  • Publication number: 20180003252
    Abstract: A piston has a piston main body including an aluminum alloy, and a covering layer formed on the outer surface of the piston main body, and the covering layer has a first plating layer including an iron-phosphorous alloy, and a second plating layer including a nickel-phosphorous alloy formed on the first plating layer.
    Type: Application
    Filed: February 18, 2016
    Publication date: January 4, 2018
    Applicants: NISSIN KOGYO CO., LTD., SHINSHU UNIVERSITY
    Inventors: Minoru OKAMOTO, Yohei TAKAHASHI, Susumu ARAI, Miyoka UEDA
  • Patent number: 8723777
    Abstract: A panel control device includes a programmable array. This programmable array operates in accordance with a configuration code and includes a plurality of first-class elements and at least one second-class element. This provides a panel control device requiring a small circuit area, being suitable for system-on-chip (SoC) mounting, and driving a liquid crystal display device having various specifications also in the future.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: May 13, 2014
    Assignee: Panasonic Corporation
    Inventors: Minoru Okamoto, Ryutaro Yamanaka, Kazuhiro Okabayashi, Yukihiro Sasagawa
  • Patent number: 8603339
    Abstract: Excess sludge production in a bioreactor of a wastewater treatment plant in which excess sludge is being produced is reduced by adding an activated sludge material having a chitinase specific activity of at least 150 Units/g-MLSS and a pectinase specific activity of at least 120 Units/g-MLSS to the bioreactor. After the addition of the activated sludge material, the bioreactor is controlled by adding the activated sludge material when any one of the chitinase activity, the pectinase activity, and the protease specific of the sludge in the bioreactor drops below the lower limits of 50 Units/L, 40 Units/L, and 0.3 Units/L, respectively.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: December 10, 2013
    Assignee: Diamond Engineering Co., Ltd.
    Inventors: Katsuhiko Maeda, Minoru Okamoto
  • Publication number: 20120293526
    Abstract: A panel control device includes a programmable array. This programmable array operates in accordance with a configuration code and includes a plurality of first-class elements and at least one second-class element. This provides a panel control device requiring a small circuit area, being suitable for system-on-chip (SoC) mounting, and driving a liquid crystal display device having various specifications also in the future.
    Type: Application
    Filed: July 27, 2012
    Publication date: November 22, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Minoru OKAMOTO, Ryutaro YAMANAKA, Kazuhiro OKABAYASHI, Yukihiro SASAGAWA
  • Patent number: 7877238
    Abstract: A data classification supporting method capable of easily discriminating a cell to which unknown data belongs and cells similar to the unknown data from each other is obtained. This classification compares cell vector data of each cell with the unknown data, decides a cell having cell vector data closest to the unknown data and cells having cell vector data secondly to nthly close to the unknown data as a minimum cell and similar cells respectively and displays a minimum cell mark and similar cell marks indicating the minimum cell and the similar cells respectively on a classification map.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: January 25, 2011
    Assignee: Sysmex Corporation
    Inventors: Kiyoaki Watanabe, Yohko Kawai, Takayuki Mitsuhashi, Dai Furuie, Minoru Okamoto
  • Publication number: 20100206808
    Abstract: Excess sludge production in a bioreactor of a wastewater treatment plant in which excess sludge is being produced is reduced by adding an activated sludge material having a chitinase specific activity of at least 150 Units/g-MLSS and a pectinase specific activity of at least 120 Units/g-MLSS to the bioreactor. After the addition of the activated sludge material, the bioreactor is controlled by adding the activated sludge material when any one of the chitinase activity, the pectinase activity, and the protease specific of the sludge in the bioreactor drops below the lower limits of 50 Units/L, 40 Units/L, and 0.3 Units/L, respectively.
    Type: Application
    Filed: August 26, 2008
    Publication date: August 19, 2010
    Applicant: DIAMOND ENGINEERING CO., LTD.
    Inventors: Katsuhiko Maeda, Minoru Okamoto
  • Patent number: 7774281
    Abstract: A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits a license request for using a function standard required for realizing the function to a license management device. The license management device receives the usage license request and correspondingly transmits an authorization for using the function standard to the program distribution device and the contents distribution device. The program distribution device transmits the program to the terminal device only when the usage authorization is received. The contents distribution device transmits the information contents to the terminal device only when the usage authorization is received.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: August 10, 2010
    Assignee: Panasonic Corporation
    Inventors: Minoru Okamoto, Katsuhiko Ueda, Shirou Yoshioka, Tetsuji Kishi
  • Patent number: 7551001
    Abstract: A plurality of logic element groups LEG11 to LEG33 respectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEG11 and LEG12, clock out terminal and clock in terminal are connected via a line while data out terminal and data in terminal are connected via a delay element 101. The logic element groups LEG11 to LEG33 are therefore independent of one another in terms of timing design. Thus, if redesign is necessary for a semiconductor integrated circuit completed with a plurality of logic element groups, only a new circuit may be designed and connected to an existing circuit, or an unnecessary logic element group may just be removed, to complete a new semiconductor integrated circuit.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: June 23, 2009
    Assignee: Panasonic Corporation
    Inventors: Tatsuya Tetsukawa, Minoru Okamoto, Shinichi Marui
  • Patent number: 7536289
    Abstract: A method of configuring an information processing system according to the present invention, in an information processing system for realizing one or a plurality of applications, comprises, a step of modeling all of the applications for each certain process level and inputting the models, a step of inputting parameters representing invariability for the inputted models, a step of using the models of the applications and the parameters representing invariability as inputted information and comparing the parameters representing invariability to a boundary condition, and a step of allocating one of the application models to programmable logic and another of the application models to an exclusive-use hardware based on a result of the comparison.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: May 19, 2009
    Assignee: Panasonic Corporation
    Inventors: Kazuhiro Okabayashi, Minoru Okamoto
  • Patent number: 7492184
    Abstract: The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced. In a programmable logic device 101 formed from programmable logical elements, there are provided first logical elements 102 and second logical elements 104 having the same logic as the first logical elements 102 but having an upper limit of operating speed designed to be lower than that of the first logical elements 102.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: February 17, 2009
    Assignee: Panasonic Corporation
    Inventors: Atsuhiro Mori, Shinichi Marui, Minoru Okamoto
  • Patent number: 7474212
    Abstract: The device will make it easy to recognize an individual object located at a specific location using radio frequency ID tags. The device includes an object having an object main body, a tag provided with the object main body, and a display section provided with the object main body to display the information corresponding to the ID information stored on the tag.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: January 6, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Nakagawa, Minoru Okamoto
  • Patent number: 7378871
    Abstract: In a programmable cell included in a first region, configuration information is stored in a volatile memory, while in a programmable cell included in a second region, configuration information is stored in a non-volatile memory. Configuration information for a sub-process common to a plurality of processes is stored in the non-volatile memory.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: May 27, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Minoru Okamoto
  • Publication number: 20080072129
    Abstract: A digital signal processor includes an instruction executer configured to execute instructions. The instruction executer determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The instruction executer outputs a processed data including the first minimum data and the second minimum data. A bit length of the first minimum data is equal to n bits in length. A bit length of the second minimum data is equal to n bits in length. A bit length of the processed data is equal to at least 2n bits in length.
    Type: Application
    Filed: October 30, 2007
    Publication date: March 20, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Ryutaro YAMANAKA, Hidetoshi SUZUKI, Hideyuki KABUO, Minoru OKAMOTO, Kevin STONE
  • Publication number: 20080061834
    Abstract: A plurality of logic element groups LEG11 to LEG33 respectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEG11 and LEG12, clock out terminal and clock in terminal are connected via a line while data out terminal and data in terminal are connected via a delay element 101. The logic element groups LEG11 to LEG33 are therefore independent of one another in terms of timing design. Thus, if redesign is necessary for a semiconductor integrated circuit completed with a plurality of logic element groups, only a new circuit may be designed and connected to an existing circuit, or an unnecessary logic element group may just be removed, to complete a new semiconductor integrated circuit.
    Type: Application
    Filed: October 2, 2006
    Publication date: March 13, 2008
    Inventors: Tatsuya Tetsukawa, Minoru Okamoto, Shinichi Marui
  • Publication number: 20080042687
    Abstract: The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced. In a programmable logic device 101 formed from programmable logical elements, there are provided first logical elements 102 and second logical elements 104 having the same logic as the first logical elements 102 but having an upper limit of operating speed designed to be lower than that of the first logical elements 102.
    Type: Application
    Filed: March 10, 2005
    Publication date: February 21, 2008
    Inventors: Atsuhiro Mori, Shinichi Marui, Minoru Okamoto
  • Patent number: 7325184
    Abstract: A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2 n bits in length.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: January 29, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ryutaro Yamanaka, Hidetoshi Suzuki, Hideyuki Kabuo, Minoru Okamoto, Kevin Mark Stone
  • Patent number: 7287149
    Abstract: An information processing method for coding a program to enable an information processing device having an instruction decoder having a reconfigurable circuit, comprises the steps of: simulating execution of the program to obtain a history of instructions executed; extracting a routine in which a number of types of codes used in at least a field among fields constituting an instruction is limited to a predetermined number or less, from the program based on the history; inserting an instruction for changing circuit configuration of the reconfigurable circuit at start and end of the routine; allocating codes so that number of times of change of bit values in a field in which the number of types of codes used are limited is reduced for the routine; and converting a program obtained in the step of inserting an instruction to codes according to the allocation for the routine.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: October 23, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minoru Okamoto, Katsuhiko Ueda
  • Patent number: 7171643
    Abstract: Adequately assigning features provided by the system to processing units having different architectures incorporated in a system LSI. An analysis unit is provided for counting the number of conditional branch statements and the number of loop control statements, the number of nestings of the conditional branch statements and the number of nestings of the loop control statements, and the number of functions required to generate the conditions of the conditional branch statements and the number of repetitions of loop control statements described in each function of a program describing system features in a high-level language.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: January 30, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Minoru Okamoto
  • Patent number: 7139968
    Abstract: A digital signal processor configured to perform a Viterbi algorithm includes an instruction fetching unit that fetches instructions and a decoding unit that decodes the instructions fetched by the instruction fetching unit. The digital signal processor also includes an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes an arithmetic logic unit configured to perform a register—register arithmetic logic operation. The arithmetic logic unit compares a first data with a second data, in parallel with a comparison of a third data with a fourth data, and the execution unit outputs new path metrics. Each of the first data, the second data, the third data, and the fourth data is one of four results obtained by adding one of two path metrics to one of two branch metrics.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: November 21, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ryutaro Yamanaka, Hidetoshi Suzuki, Hideyuki Kabuo, Minoru Okamoto, Kevin Mark Stone