Patents by Inventor Minoru Sudou

Minoru Sudou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8664925
    Abstract: Provided is a voltage regulator having low current consumption, which is capable of preventing a reverse current from flowing thereto from an output terminal (122), irrespective of a magnitude of a voltage of a VDD terminal (121). The voltage regulator has a circuit configuration in which voltage dividing resistors are not used for a comparator circuit for comparing the voltage of the VDD terminal (121) with a voltage of the output terminal (122), to thereby achieve lower current consumption.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: March 4, 2014
    Assignee: Seiko Instruments Inc.
    Inventors: Minoru Sudou, Yotaro Nihei
  • Patent number: 8198875
    Abstract: Provided is a voltage regulator capable of securely preventing a reverse current from an output terminal (122) with lower current consumption, irrespective of magnitude of a voltage of a VDD terminal (121). Such a configuration is adopted that the voltage of the VDD terminal (121) and a voltage of the output terminal (122) of the voltage regulator are compared with each other with the use of a voltage generated between a transistor and a constant current circuit, to thereby reduce current consumption of a backup battery. Besides, such a configuration is also adopted that a gate of an output transistor is connected with the output terminal (122) based on an output of a comparator circuit, to thereby prevent the reverse current securely.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: June 12, 2012
    Assignee: Seiko Instruments Inc.
    Inventor: Minoru Sudou
  • Patent number: 8188719
    Abstract: Provided is a voltage regulator capable of stable operation under a light load so as to cover a wide range of load capacitances. The voltage regulator includes a circuit for charging a phase compensation capacitor for the voltage regulator, and a zero due to a resistor (104) and a capacitor (106) appears at low frequency.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: May 29, 2012
    Assignee: Seiko Instruments Inc.
    Inventor: Minoru Sudou
  • Publication number: 20110291636
    Abstract: Provided is a voltage regulator capable of stable operation under a light load so as to cover a wide range of load capacitances. The voltage regulator includes a circuit for charging a phase compensation capacitor for the voltage regulator, and a zero due to a resistor (104) and a capacitor (106) appears at low frequency.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 1, 2011
    Inventor: Minoru Sudou
  • Publication number: 20110169465
    Abstract: Provided is a voltage regulator having low current consumption, which is capable of preventing a reverse current from flowing thereto from an output terminal (122), irrespective of a magnitude of a voltage of a VDD terminal (121). The voltage regulator has a circuit configuration in which voltage dividing resistors are not used for a comparator circuit for comparing the voltage of the VDD terminal (121) with a voltage of the output terminal (122), to thereby achieve lower current consumption.
    Type: Application
    Filed: March 21, 2011
    Publication date: July 14, 2011
    Inventors: Minoru Sudou, Yotaro Nihei
  • Publication number: 20110062921
    Abstract: Provided is a voltage regulator capable of securely preventing a reverse current from an output terminal (122) with lower current consumption, irrespective of magnitude of a voltage of a VDD terminal (121). Such a configuration is adopted that the voltage of the VDD terminal (121) and a voltage of the output terminal (122) of the voltage regulator are compared with each other with the use of a voltage generated between a transistor and a constant current circuit, to thereby reduce current consumption of a backup battery. Besides, such a configuration is also adopted that a gate of an output transistor is connected with the output terminal (122) based on an output of a comparator circuit, to thereby prevent the reverse current securely.
    Type: Application
    Filed: September 15, 2009
    Publication date: March 17, 2011
    Applicant: Seiko Instruments Inc.
    Inventor: Minoru Sudou
  • Patent number: 7737782
    Abstract: Provided is a CMOS operational amplifier circuit that can operate with low noise, with low current consumption, and with stability. A cascode bias voltage of a folded cascode circuit in the CMOS operational amplifier circuit is modulated by a current at an input differential stage, thereby enabling operation with low noise, with low current consumption, and with stability.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: June 15, 2010
    Assignee: Seiko Instruments Inc.
    Inventor: Minoru Sudou
  • Patent number: 7394138
    Abstract: A capacitance-type dynamic-quantity sensor has a silicon substrate having etched recessed upper and lower surface portions forming a weight supported by beam portions and mounted to undergo displacement due to an applied external dynamic quantity such as acceleration or angular velocity. An upper glass substrate is bonded to a part of the upper surface of the silicon substrate and is laminated with a first fixed electrode disposed opposite to and spaced apart from the weight with a first space therebetween formed by the etched recessed upper surface portion of the silicon substrate. A lower glass substrate is bonded to a part of the lower surface of the silicon substrate and is laminated with a second fixed electrode disposed opposite to and spaced apart from the weight with a second space therebetween formed by the etched recessed lower surface portion of the silicon substrate.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: July 1, 2008
    Assignee: Seiko Instruments Inc.
    Inventors: Kenji Katou, Minoru Sudou, Hitsuo Yarita
  • Patent number: 7294895
    Abstract: A capacitive dynamic quantity sensor whose size is small and whose reliability and mass productivity are high is provided. In order to realize signal transmission from a lower electrode to an upper electrode, silicon columns which are electrically isolated from one another but not mechanically isolated from one another are formed to connect both electrodes.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: November 13, 2007
    Assignee: Seiko Instruments Inc.
    Inventors: Mitsuo Yarita, Minoru Sudou, Kenji Kato
  • Patent number: 7236425
    Abstract: A charge pump circuit is provided which outputs a high voltage by using a boosting circuit with a smaller number of stages. A diode is used to give a back-gate voltage for a MOS transistor composing the charge pump circuit, thereby minimizing a reduction in a boosted voltage due to an increase in the threshold voltage of the MOS transistor. In addition, a second MOS transistor is provided between the back gate of the MOS transistor and the ground (GND) such that in-phase clock signals are inputted to the gate of the second MOS transistor and the capacitor thereof.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: June 26, 2007
    Assignee: Seiko Instruments Inc.
    Inventor: Minoru Sudou
  • Patent number: 7224193
    Abstract: A CV conversion circuit capable of measuring a plurality of capacitances with a simple circuit is provided. A time-division signal is applied to each capacitor, whereby a plurality of capacitances of the capacitors can be measured in series by a circuit with a small number of components.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: May 29, 2007
    Assignee: Seiko Instruments Inc.
    Inventors: Minoru Sudou, Mitsuo Yarita, Kenji Kato
  • Patent number: 7216541
    Abstract: A capacitive sensor for measuring a dynamical quantity based on a change in capacitance has a semiconductor substrate having a weight supported by beams so as to undergo displacement according to the dynamical quantity. The semiconductor substrate is sandwiched between glass substrates on which fixed electrodes are disposed in a position facing the weight with minute gaps existing between the glass substrates and the weight. A substrate electrode is disposed on one of the glass substrates and contacts a part of the semiconductor substrate. A recess having a size equal to or larger than a contact area in which the semiconductor substrate contacts the substrate electrode is formed in the semiconductor substrate, and a contact electrode is disposed in the recess in contact with the substrate electrode.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: May 15, 2007
    Assignee: Seiko Instruments Inc.
    Inventors: Kenji Kato, Minoru Sudou, Mitsuo Yarita
  • Patent number: 7034581
    Abstract: A voltage detecting circuit that has a stable output even when a battery voltage is low includes first and second terminals connected across poles of a battery, a reference voltage generating circuit, and a comparator for comparing values of the reference voltage and voltage across the terminals. A first output circuit is connected between the first and second terminals to output a first output signal on the basis of the comparison result, a second output circuit outputs a second output signal that changes in value based on a voltage of the battery and on the basis of signals at the first and second terminals, and an output terminal outputs the first and second output signals.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: April 25, 2006
    Assignee: Seiko Instruments Inc.
    Inventor: Minoru Sudou
  • Publication number: 20060013047
    Abstract: A charge pump circuit is provided which outputs a high voltage by using a boosting circuit with a smaller number of stages. A diode is used to give a back-gate voltage for a MOS transistor composing the charge pump circuit, thereby minimizing a reduction in a boosted voltage due to an increase in the threshold voltage of the MOS transistor. In addition, a second MOS transistor is provided between the back gate of the MOS transistor and the ground (GND) such that in-phase clock signals are inputted to the gate of the second MOS transistor and the capacitor thereof.
    Type: Application
    Filed: July 5, 2005
    Publication date: January 19, 2006
    Inventor: Minoru Sudou
  • Publication number: 20050253628
    Abstract: A CV conversion circuit capable of measuring a plurality of capacitances with a simple circuit is provided. A time-division signal is applied to each capacitor, whereby a plurality of capacitances of the capacitors can be measured in series by a circuit with a small number of components.
    Type: Application
    Filed: May 11, 2005
    Publication date: November 17, 2005
    Inventors: Minoru Sudou, Mitsuo Yarita, Kenji Kato
  • Publication number: 20050242413
    Abstract: A capacitive dynamic quantity sensor whose size is small and whose reliability and mass productivity are high is provided. In order to realize signal transmission from a lower electrode to an upper electrode, silicon columns which are electrically isolated from one another but not mechanically isolated from one another are formed to connect both electrodes.
    Type: Application
    Filed: April 5, 2005
    Publication date: November 3, 2005
    Inventors: Mitsuo Yarita, Minoru Sudou, Kenji Kato
  • Publication number: 20050155428
    Abstract: A capacitive sensor for measuring a dynamical quantity based on a change in capacitance is disclosed: a semiconductor substrate 2 having the weight 5 which is supported by beams 4 and moves according to the dynamical quantity; and a glass substrate 1,3 on which fixed electrodes 11 are disposed in a position facing the weight with minute gaps 6,7 from the weight 5, and a substrate electrode 12 contacting with a part of the semiconductor substrate are laminated; wherein a recess having a size equal to or larger than a contact area is formed in an area within the semiconductor substrate 2 in which the semiconductor substrate 2 contacts the substrate electrode 12.
    Type: Application
    Filed: January 20, 2005
    Publication date: July 21, 2005
    Inventors: Kenji Kato, Minoru Sudou, Mitsuo Yarita
  • Publication number: 20040263186
    Abstract: The present invention provides a capacitance type dynamic quantity sensor which is miniature and inexpensive. A capacitance detection electrode formed on a lower glass plate is made conductive up to an outer surface of an upper glass plate via through-holes formed so as to vertically and perfectly extend through the upper glass plate, and solder balls. Thus, the electrodes to be connected to an external substrate are collectively provided on the outer surface of the upper glass plate to allow the capacitance type dynamic quantity sensor to be directly mounted to an external substrate.
    Type: Application
    Filed: May 12, 2004
    Publication date: December 30, 2004
    Inventors: Mitsuo Yarita, Minoru Sudou, Kenji Katou
  • Patent number: 6836102
    Abstract: A voltage regulator which suppresses an inrush current at the time of power application has input and output terminals, a power supply connected to the input terminal, a switch circuit connected to the power supply, a coil connected between the switch circuit and the output terminal, a rectifying device connected in series between the coil and the output terminal, an output capacitor connected to the output terminal, a switching element connected between the coil and the rectifying device, a driving circuit for driving the switching element, a transistor connected between the power supply and the coil, and a control circuit connected to the transistor for gradually varying an ON resistance of the transistor from a relatively large value immediately after the switch circuit is turned on to a relatively small value a predetermined time thereafter to limit a rush current flowing into the output capacitor from the power supply.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: December 28, 2004
    Assignee: Seiko Instruments Inc.
    Inventor: Minoru Sudou
  • Publication number: 20040246648
    Abstract: To provide a capacitance-type dynamic-quantity sensor capable of reducing a variation in detection sensitivity, free of peeling of an electrode or disconnection thereof, and excellent in reliability, and a manufacturing method therefor. In the capacitance-type dynamic-quantity sensor, a semiconductor substrate where an oscillator is to be formed is processed with a high precision from its front and rear sides to define minute spaces between the oscillator, and flat upper glass substrate and lower glass substrate on each of which an electrode is to be laminated, thereby reducing a variation in detection sensitivity and suppressing peeling of the electrode and disconnection thereof.
    Type: Application
    Filed: May 18, 2004
    Publication date: December 9, 2004
    Inventors: Kenji Katou, Minoru Sudou, Hitsuo Yarita