Patents by Inventor Minoru Sudou

Minoru Sudou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6828763
    Abstract: A voltage regulator comprises a differential amplifier for comparing an output of a reference voltage circuit with an output of a voltage dividing circuit and outputting a first signal and a phase compensating circuit having a resistor and a capacitor connected in series. A MOS transistor is connected between a power supply and the phase compensating circuit and has a gate electrode connected to receive the output of the differential amplifier and a grounded source. A constant current circuit is connected between the MOS transistor and ground, and an output transistor having a gate electrode connected to receive a second signal output from a connection point between the MOS transistor and the phase compensating circuit is connected between the power supply and the voltage dividing circuit.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: December 7, 2004
    Assignee: Seiko Instruments Inc.
    Inventors: Minoru Sudou, Kenji Kanou
  • Publication number: 20040130306
    Abstract: Provided is a voltage regulator which has a high speed response property in a low consumption current and is stably operable in a low output capacitance. The voltage regulator has: a differential amplifier for comparing an output of a reference voltage circuit with an output of a voltage dividing circuit and outputting a first signal; a phase compensating circuit in which a resistor and a capacitor are connected in series; a MOS transistor in which an output of the differential amplifier is inputted to a gate electrode, which is connected between a power supply and the phase compensating circuit, and in which a source is grounded; a constant current circuit connected between the MOS transistor and a ground; and an output transistor in which a second signal output from a connection point between the MOS transistor and the phase compensating circuit is inputted to a gate electrode and which is connected between the power supply and the voltage dividing circuit.
    Type: Application
    Filed: July 24, 2003
    Publication date: July 8, 2004
    Inventors: Minoru Sudou, Kenji Kanou
  • Publication number: 20040113630
    Abstract: To prevent the output voltage of a voltage detecting circuit from becoming inconstant when the voltage of a battery is low.
    Type: Application
    Filed: November 13, 2003
    Publication date: June 17, 2004
    Inventor: Minoru Sudou
  • Patent number: 6727556
    Abstract: A semiconductor device has a semiconductor element formed on a semiconductor substrate and a first insulating film having contact holes. The semiconductor element has a gate electrode, a source region and a drain region. The semiconductor element also has metal wirings each for connecting a respective one of the contact holes to the gate electrode, the source region and the drain region of the semiconductor element. A second insulating film is formed on the first insulating film and the metal wirings. The second insulating film has a chemical-mechanical polished portion defining a flattened upper surface of the second insulating film. Resistors are formed on and are disposed directly in contact with the flattened upper surface of the second insulating film and are connected in series to form a bleeder resistor circuit or a ladder circuit.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: April 27, 2004
    Assignee: Seiko Instruments Inc.
    Inventors: Mika Shiiki, Minoru Sudou
  • Publication number: 20030062880
    Abstract: There is provided a booster type SW regulator in which an inrush current at a time of power application is suppressed. A MOS transistor is inserted between a power supply and a coil of the booster type SW regulator, and an ON resistance of the MOS transistor is made large at a time of power application.
    Type: Application
    Filed: September 17, 2002
    Publication date: April 3, 2003
    Inventor: Minoru Sudou
  • Publication number: 20020020879
    Abstract: To provide a miniaturized and integrated semiconductor device with a resistor structuring a ladder circuit or the like. An insulating film is formed on a semiconductor substrate formed with a semiconductor element, and leveling of the top surface is performed by CMP or the like. Then, a resistor is formed not only on a field region through the leveled insulating film, but also on an active region where the semiconductor element is formed. Further, an insulating film is further formed on the resistor, and electrodes are formed in the resistor through contact holes.
    Type: Application
    Filed: July 26, 2001
    Publication date: February 21, 2002
    Inventors: Mika Shiiki, Minoru Sudou