Patents by Inventor Minoru Taguchi

Minoru Taguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5218224
    Abstract: Buried layers of a second conductivity type are formed in a plurality of portions of a surface region of a semiconductor substrate of a first conductivity type, and an epitaxial layer of the first conductivity type is formed on the buried layers and the semiconductor substrate. A plurality of well regions of the second conductivity type are formed in the epitaxial layer in contact with the buried layers, and a region of the second conductivity type with a high impurity concentration is formed in one of the well regions in contact with the buried layers. A field insulating layer is formed on a surface region of the semiconductor substrate between the well regions. An impurity is ion-implanted in a portion substantially immediately below the field insulating film a plurality of times to form inversion preventing layers of the first conductivity type having a plurality of impurity concentration peaks. Active elements are formed in the epitaxial layer of the first conductivity type and the well regions.
    Type: Grant
    Filed: August 13, 1991
    Date of Patent: June 8, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Minoru Taguchi
  • Patent number: 5198880
    Abstract: For providing a semiconductor integrated circuit device including CCD type, bipolar type and MOS type integrated circuits in only one chip, island-shaped epitaxial layers of opposite conductivity type are disposed in a semiconductor substrate of one conductivity type having a low impurity concentration. A field oxide layer is provided so as to surround a periphery of an exposed surface of each epitaxial layer. A buried layer of opposite conductivity type having a high impurity concentration is is interposed between the semiconductor substrate and each epitaxial layer in such a manner that at least one edge thereof terminates to the lower surfaace of the field oxide layer. The CCD type integrated circuit is provided in the semiconductor substrate, and the bipolar type and MOS type integrated circuits are arranged in the epitaxial layers.
    Type: Grant
    Filed: October 28, 1991
    Date of Patent: March 30, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minoru Taguchi, Hiroshi Mochizuki
  • Patent number: 5184203
    Abstract: A semiconductor device having a semiconductor substrate of a first conductivity type, an epitaxial layer of a second conductivity type formed on a major surface of the semiconductor subtrate, an isolation layer of the first conductivity type formed in the epitaxial layer and extending from a surface thereof to the major surface of the semiconductor substrate. The isolation layer divides the epitaxial layer into first, second, and third islands. The device further has two wells of the first conductivity type, formed in the first and second islands, respectively, and extending to the substrate, a charge transfer device having a back gate formed of the first well, an insulated-gate FET of the first conductivity type, having a back gate formed of the second island, an insulated-gate FET of the second conductivity type, having a back gate formed of the second well, and a bipolar transistor having a collector formed of the third island.
    Type: Grant
    Filed: January 16, 1991
    Date of Patent: February 2, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Minoru Taguchi
  • Patent number: 5151711
    Abstract: An automobile antenna of a rod shape comprises an antenna element and a hollow cylindrical member of a resin fitted on the circumference of the antenna element. The hollow cylindrical member includes a plurality of hollow cylindrical units that may be coupled together or may be spaced apart. The cylindrical member has a ridge or ridges in the form of a spiral or ring. The ridge functions to generate a turbulent flow of air when the automobile runs at a high speed, so that a whistling sound generated by the wind blow may be eliminated. The method of making an antenna uses two offset molds having a plurality of cavities by the provision of spaced apart partitions, which also support the antenna element. A molding material is supplied into the cavities so that the ridges-bearing cylindrical member and the antenna element may be fabricated as one unit.
    Type: Grant
    Filed: September 24, 1990
    Date of Patent: September 29, 1992
    Assignee: Harada Industry Co., Ltd.
    Inventor: Minoru Taguchi
  • Patent number: 4994888
    Abstract: A semiconductor device comprising a semiconductor chip formed of a substrate of a first conductivity type and an epitaxial layer of the first conductivity type formed on the substrate, a charge transfer device section formed in the epitaxial layer and driven by a given clock, and a preset region of a second conductivity type formed adjacent to the charge transfer device section in the semiconductor ship. The preset region includes a first layer of the second conductivity type formed in a boundary portion between the substrate and the epitaxial layer, a second layer of the second conductivity type formed on the first layer the epitaxial layer, and a third layer of the second conductivity type formed on the second layer in the epitaxial layer to reach the surface of the substrate. The maximum value of the second conductivity type impurity concentration of the third layer is set smaller than the maximum value of the second conductivity type impurity concentration of the first layer.
    Type: Grant
    Filed: May 18, 1990
    Date of Patent: February 19, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minoru Taguchi, Kazuo Kihara
  • Patent number: 4968822
    Abstract: A 21-alkoxysteroid compound represented by the formula ##STR1## wherein R.sup.1 is an alkyl group having 1 to 4 carbon atoms or a methylthiomethyl group, R.sup.2 is an alkanoyl group having 2 to 7 carbon atoms, and a wavy line indicates the .alpha.- or .beta.-configuration has anti-inflammatory activity.
    Type: Grant
    Filed: December 5, 1988
    Date of Patent: November 6, 1990
    Assignee: Taisho Pharmaceutical Co., Ltd.
    Inventors: Morihiro Mitsukuchi, Tomoyuki Ikemoto, Minoru Taguchi, Katsuo Hatayama, Kaoru Sota
  • Patent number: 4963435
    Abstract: A wire with a coated layer for bonding to a joint body by ultrasonic vibration, the coated layer of said wire comprising urethane resin having formulated therein a brominated epoxy resin.
    Type: Grant
    Filed: December 2, 1988
    Date of Patent: October 16, 1990
    Assignees: Hitachi, Ltd., Hitachi Computer Peripherals Co., Ltd., Hitachi Cable, Ltd.
    Inventors: Shigeo Hara, Setsuo Sekine, Toshio Suzuki, Minoru Taguchi, Akio Mitsuoka, Yoshiyuki Tetsu
  • Patent number: 4935800
    Abstract: This invention discloses a semiconductor integrated circuit in which an analog circuit and a digital circuit are formed on a single chip. The semiconductor integrated circuit includes a p-type semiconductor region, an n.sup.+ -type buried region formed on the p-type semiconductor region, an n-type semiconductor region formed on the n.sup.+ -type buried region, a first isolation portion, extending through the n-type semiconductor region and the n.sup.+ -type buried region and reaching the p-type semiconductor region, for isolating adjacent transistors in an analog circuit formed on the n-type semiconductor region, and a second isolation portion, formed in the n-type semiconductor region, for isolating adjacent transistors in the n-type semiconductor region.
    Type: Grant
    Filed: February 21, 1989
    Date of Patent: June 19, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Minoru Taguchi
  • Patent number: 4841044
    Abstract: Cephalosporin derivatives represented by the general formula ##STR1## wherein R is a hydrogen atom or a lower alkyl group having 1 to 4 carbon atoms, R' is a hydrogen atom, a lower alkyl group having 1 to 4 carbon atoms, a cycloalkyl group having 5 or 6 carbon atoms or a benzyl group, or R and R' together with the nitrogen atom to which they are attached form a tetrahydropyridinyl group, a morpholinyl group or pyrroridinyl group, and the non-toxic salts thereof are disclosed. These compounds are useful as antibacterial agents.
    Type: Grant
    Filed: December 18, 1986
    Date of Patent: June 20, 1989
    Assignee: Taisho Pharmaceutical Co., Ltd.
    Inventors: Yoshiaki Watanabe, Chihiro Yokoo, Masami Goi, Akira Onodera, Mitsuo Murata, Hiroshi Fukushima, Minoru Taguchi, Kaoru Sota
  • Patent number: 4554046
    Abstract: A method for selectively etching a high impurity concentration semiconductor layer by making use of a difference in impurity concentration is disclosed. According to this method, the high impurity concentration semiconductor layer is exposed to an aqueous solution of a hydrogen fluoride-nitric acid-acetic acid-based etching solution while being subjected to ultrasonic-vibration.
    Type: Grant
    Filed: September 19, 1984
    Date of Patent: November 19, 1985
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minoru Taguchi, Gen Sasaki
  • Patent number: 4539742
    Abstract: A semiconductor device wherein collector connecting wiring made of for example n.sup.+ -type polycrystalline silicon layer is formed by an anisotropic etching which simultaneously engrave a groove in a semiconductor substrate. A collector layer is formed on a non-etched projection, while base contact hole is formed in the lower portion of the groove. Therefore, the base contact hole is not contacted with collector layer, thus preventing the flow of a leakage current and short-circuiting therebetween.
    Type: Grant
    Filed: June 18, 1982
    Date of Patent: September 10, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Koichi Kanzaki, Minoru Taguchi
  • Patent number: 4404737
    Abstract: A method for manufacturing a semiconductor integrated circuit includes diffusing an impurity of a second conductivity type into polycrystalline silicon layers formed on a first conductivity region in a substrate to form second conductivity regions, the polycrystalline silicon layers constituting first electrode wirings to the second conductivity regions; forming a thick oxidation film on the polycrystalline silicon layers and a thin oxidation film on the exposed surface of the substrate by a heat oxidation treatment; and removing the thin oxidation film to form a second electrode wiring to the first conductivity region, said second electrode wiring being insulated from the polycrystalline silicon layers by the thick oxidation film. The method provides integrated circuits such as I.sup.2 L circuits which are capable of high speed operation and a high packaging density.
    Type: Grant
    Filed: November 28, 1980
    Date of Patent: September 20, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Koichi Kanzaki, Minoru Taguchi
  • Patent number: 4404738
    Abstract: An integrated circuit device is provided in which an I.sup.2 L element and linear transistor are formed on a single chip such that they coexist. In this device, the base and collector regions of a vertical transistor of the I.sup.2 L element are formed such that they are deeper than the base and emitter regions of the linear transistor.
    Type: Grant
    Filed: September 25, 1981
    Date of Patent: September 20, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Gen Sasaki, Minoru Taguchi, Koichi Kanzaki, Akihiko Furukawa
  • Patent number: 4377903
    Abstract: An oxide layer is partially formed on an n-type region surrounded by a field oxide region. A base region of a switching transistor is formed in the n-type region using as a mask the oxide layer. Arsenic-doped polysilicon layers are selectively formed simultaneously on the surfaces of the oxide layer and the base region. Using the polysilicon layers as a mask, the emitter and collector regions of an injector transistor and the external base region of a switching transistor are formed in the n-type region and the base region respectively. Arsenic doped into the polysilicon layers is diffused into the base region, so that the collector regions of the switching transistor are self-aligned with the polysilicon layers.
    Type: Grant
    Filed: February 18, 1981
    Date of Patent: March 29, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Koichi Kanzaki, Minoru Taguchi