Abstract: A system, method, and computer product for high-speed multiplication of binary numbers. A multiplier X is first encoded, and the encoded multiplier is then used in a multiplication process that yields the product. The encoding is performed in a manner that allows the actual multiplication process to proceed quickly. X is copied into a variable Z. Z is then manipulated to form the coded version of the multiplier. The bits of the multiplier X are read two at a time, starting with the least significant two bits. If the bit pair Xi+1Xi is equal to 11, then 1 is added to Zi+2. The process continues for successive non-overlapping pairs of bits, until the most significant three bits of X are reached. These last three bits are encoded using a table look-up process.

Abstract: A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0?, x1?} such that a number of 1's at bit x0? over time is within ?1 of a number of 1's at bit x1?. At least two 4-bit vector shufflers input the vectors {x0?, x1?}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0?, x1?} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0?, x1?} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.

Abstract: A system and method is provided for stabilizing high order sigma delta modulators. The system includes an integrator having a limiter in the feedback path of the integrator. The integrator combines an input signal with a feedback signal generated by the limiter to produce an integrated output signal. The output signal is output to the next component of the sigma delta modulator. In addition, the output signal is fed back through the limiter. When an output signal received in the feedback path by the limiter exceeds the threshold value of the limiter, the limiter is activated and clamps the output signal to produce a limited signal. The limited signal is combined with the input signal to the integrator to produce the output signal.

Abstract: An error feedback circuit includes a first summer receiving an analog input signal and a feedback signal and outputting a summed signal. A quantizer receives the summed signal and outputs a quantized output signal. A limiter receives the summed signal and outputs a limited summed signal. The limiter limits the limited summed signal to ?* (maximum value of input signal), ?>1. A second summer receives the limited summed signal and the output signal and outputs an error signal. A filter receives the error signal and outputting the feedback signal. Typically, 1.0<?<2.0, more preferably 1.4<?<1.6. The filter has a transfer function of H1(z)=2z?1?z?2.

Abstract: An error feedback circuit includes a first summer receiving an analog input signal and a feedback signal and outputting a summed signal. A quantizer receives the summed signal and outputs a quantized output signal. A limiter receives the summed signal and outputs a limited summed signal. The limiter limits the limited summed signal to ?* (maximum value of input signal), ?>1. A second summer receives the limited summed signal and the output signal and outputs an error signal. A filter receives the error signal and outputting the feedback signal. Typically, 1.0<?<2.0, more preferably 1.4<?<1.6. The filter has a transfer function of H1(z)=2z?1?z?2.

Abstract: A filter structure used with a dynamic element matching encoder for a sigma-delta digital-to-analog converter is presented. A sampled input sequence having undesired frequency tones is divided into even and odd data sub-sequences. Each of the sub-sequences is processed by a dynamic element matching encoder, with a transfer function H(z?1). The resulting processed sub-sequences are combined into an output sequence. The undesired frequency tones are substantially reduced in the output sequence.

Abstract: Provided are a system and method for implementing a multirate analog finite impulse response (FIR) filter. A system of the present invention includes a modulator having a first adder and a quantizer. The first adder includes an output port, and the quantizer includes (i) an input port coupled to the first adder output port and (ii) a quantizer output port. A second adder is also included, having one input port coupled to the first adder output port and another input port coupled to the quantizer output port. Also included are at least two two-unit delays, a first of the two-unit delays having an input port coupled to an output port of the second adder, and an output port coupled to an input port of the second of the two-unit delays. An output port of the second two-unit delays is coupled to a first input port of the first adder.

Abstract: A decimation system comprising a plurality, L, of cascaded Finite Impulse Response (FIR) decimation filters. Each decimation filter has a transfer function of the form H(z)=(1+z?1)N, where N is an integer. Each FIR decimation filter performs decimation by a common factor I. The cascaded FIR decimation filters together achieve a decimation result substantially identical to that of an Nth-order CIC filter (that is, a CIC filter having N integrator stages) that performs decimation by a factor IL.

Abstract: Limit-cycle oscillations are caused by the compounding of quantization errors that occurs when previous digital filter outputs are used as inputs to the digital filter for the current operation. Where a signal in a digital waveform has become a constant common value applied to the input of the digital filter (indicative that the digital waveform has suspended conveyance of data), limit-cycle oscillations often appear as “random” outputs, with values different from the common value, that occur long after the signal in the digital waveform has become the constant common value. Limit-cycle oscillations are manifested as noise in the filtered digital waveform. Such noise hampers the ability of the system to extract the signal from the filtered digital waveform. The present invention identifies the occurrence of a limit-cycle oscillation as an output different from the common value. The identified limit-cycle oscillation is set equal to the common value.

Abstract: In an audio processing device, a method and system for improved CODEC with polyringer are provided. An audio CODEC may comprise an audio ADC, an audio DAC, and a sidetone generator. Data from an external microphone may be processed by an audio ADC and may be sent to a processor that may be adapted to perform digital signal processing operations. The audio DAC may receive from the processor digital audio and polyphonic ringer data and may process the digital audio and polyphonic ringer data through separate digital filters and digital interpolators. The audio DAC may add the processed digital audio and polyphonic ringer data before analog conversion. The audio DAC may perform analog conversion by utilizing a delta-sigma demodulator, a current-based DAC, and a switched-capacitor filter. The converted data may be filtered with an RC filter and may be utilized to drive an external speaker or earpiece.

Abstract: In a wireless device, a method and system for a baseband receiver interface including analog and digital components are provided. An analog or a digital interface may be selected for a I/Q data signal received from a front-end receiver. The analog interface may be a conventional RF or a VLIF interface. The I/Q data signal may be digitized when received from the analog interface and saturation detection may be used during digitization of the I/Q data signal. When the analog interface is the VLIF interface, a derotator may be used to remove the VLIF frequency. The derotator may be based on a CORDIC algorithm. The I/Q data signal may be converted from serial to parallel format when received from the digital interface. The received I/Q data signal may be decimated before transferred to a baseband processor.

Abstract: An error feedback circuit includes a first summer receiving an analog input signal and a feedback signal and outputting a summed signal. A quantizer receives the summed signal and outputs a quantized output signal. A limiter receives the summed signal and outputs a limited summed signal. The limiter limits the limited summed signal to ?*(maximum value of input signal), ?>1. A second summer receives the limited summed signal and the output signal and outputs an error signal. A filter receives the error signal and outputting the feedback signal. Typically, 1.0<?<2.0, more preferably 1.4<?<1.6. The filter has a transfer function of H1(z)=2z?1?z?2.

Abstract: Provided are a system and method for implementing a multirate analog finite impulse response (FIR) filter. A system of the present invention includes a modulator having a first adder and a quantizer. The first adder includes an output port, and the quantizer includes (i) an input port coupled to the first adder output port and (ii) a quantizer output port. A second adder is also included, having one input port coupled to the first adder output port and another input port coupled to the quantizer output port. Also included are at least two two-unit delays, a first of the two-unit delays having an input port coupled to an output port of the second adder, and an output port coupled to an input port of the second of the two-unit delays. An output port of the second two-unit delays is coupled to a first input port of the first adder.

Abstract: A codifier/decodifier (CODEC) filter circuit (250) connected in a subscriber line interface circuit (202) includes a transmit section (264, 262, 260) for converting differential voltage audio transmit signals representing voice transmissions from the subscriber instrument (202) into encoded digital data for transmission to the digital switching network. A receive section (254, 252) coupled between the digital switching network and subscriber instrument (202) within CODEC (250) for converting encoded digital data representing voice signals switched through the digital switching network to differential voltage audio receive signals for transmission to the subscriber instrument (202). The subscriber loop and subscriber instrument (202) reflect the digital voltage audio signals to the transmit section (264, 262, 260).

Abstract: A filter structure used with a dynamic element matching encoder for a sigma-delta digital-to-analog converter is presented. A sampled input sequence having undesired frequency tones is divided into even and odd data sub-sequences. Each of the sub-sequences is processed by a dynamic element matching encoder, with a transfer function H(z?1). The resulting processed sub-sequences are combined into an output sequence. The undesired frequency tones are substantially reduced in the output sequence.

Abstract: A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0?, x1?} such that a number of 1's at bit x0? over time is within ?1 of a number of 1's at bit x1?. At least two 4-bit vector shufflers input the vectors {x0?, x1?}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0?, x1?} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0?, x1?} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.

Abstract: A filter structure used with a dynamic element matching encoder for a sigma-delta digital-to-analog converter is presented. A sampled input sequence having undesired frequency tones is divided into even and odd data sub-sequences. Each of the sub-sequences is processed by a dynamic element matching encoder, with a transfer function H(z?1). The resulting processed sub-sequences are combined into an output sequence. The undesired frequency tones are substantially reduced in the output sequence.

Abstract: A system and method is provided for stabilizing high order sigma delta modulators. The system includes an integrator having a limiter in the feedback path of the integrator. The integrator combines an input signal with a feedback signal generated by the limiter to produce an integrated output signal. The output signal is output to the next component of the sigma delta modulator. In addition, the output signal is fed back through the limiter. When an output signal received in the feedback path by the limiter exceeds the threshold value of the limiter, the limiter is activated and clamps the output signal to produce a limited signal. The limited signal is combined with the input signal to the integrator to produce the output signal.

Abstract: Provided are a system and method for implementing a multirate analog finite impulse response (FIR) filter. A system of the present invention includes a modulator having a first adder and a quantizer. The first adder includes an output port, and the quantizer includes (i) an input port coupled to the first adder output port and (ii) a quantizer output port. A second adder is also included, having one input port coupled to the first adder output port and another input port coupled to the quantizer output port. Also included are at least two two-unit delays, a first of the two-unit delays having an input port coupled to an output port of the second adder, and an output port coupled to an input port of the second of the two-unit delays. An output port of the second two-unit delays is coupled to a first input port of the first adder.

Abstract: A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0?, x1?} such that a number of 1's at bit x0? over time is within ?1 of a number of 1's at bit x1?. At least two 4-bit vector shufflers input the vectors {x0?, x1?}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0?, x1?} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0?, x1?} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.