Abstract: A filter structure used with a dynamic element matching encoder for a sigma-delta digital-to-analog converter is presented. A sampled input sequence having undesired frequency tones is divided into even and odd data sub-sequences. Each of the sub-sequences is processed by a dynamic element matching encoder, with a transfer function H(z−1). The resulting processed sub-sequences are combined into an output sequence. The undesired frequency tones are substantially reduced in the output sequence.

Abstract: A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0′, x1′} such that a number of 1's at bit x0′ over time is within ±1 of a number of 1's at bit x1′. At least two 4-bit vector shufflers input the vectors {x0′, x1′}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0′, x1′} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0′, x1′} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.

Abstract: A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0′, x1′} such that a number of 1's at bit x0′ over time is within ∀1 of a number of 1's at bit x1′. At least two 4-bit vector shufflers input the vectors {x0′, x1′}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0′, x1′} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0′, x1′} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.

Abstract: A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0′, x1′} such that a number of 1's at bit x0′ over time is within ±1 of a number of 1's at bit x1′. At least two 4-bit vector shufflers input the vectors {x0′, x1′}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0′, x1′} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0′, x1′} in the same manner as the bit shufflers operate on the bits x0 and x1. The current, state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.

Abstract: A filter structure used with a dynamic element matching encoder for a sigma-delta digital-to-analog converter is presented. A sampled input sequence having undesired frequency tones is divided into even and odd data sub-sequences. Each of the sub-sequences is processed by a dynamic element matching encoder, with a transfer function H(z−1). The resulting processed sub-sequences are combined into an output sequence. The undesired frequency tones are substantially reduced in the output sequence.

Abstract: A system, method, and computer product for high-speed multiplication of binary numbers. A multiplier X is first encoded, and the encoded multiplier is then used in a multiplication process that yields the product. The encoding is performed in a manner that allows the actual multiplication process to proceed quickly. X is copied into a variable Z. Z is then manipulated to form the coded version of the multiplier. The bits of the multiplier X are read two at a time, starting with the least significant two bits. If the bit pair Xi+1Xi is equal to 11, then 1 is added to Zi+2. The process continues for successive non-overlapping pairs of bits, until the most significant three bits of X are reached. These last three bits are encoded using a table look-up process.

Abstract: Limit-cycle oscillations are caused by the compounding of quantization errors that occurs when previous digital filter outputs are used as inputs to the digital filter for the current operation. Where a signal in a digital waveform has become a constant common value applied to the input of the digital filter (indicative that the digital waveform has suspended conveyance of data), limit-cycle oscillations often appear as “random” outputs, with values different from the common value, that occur long after the signal in the digital waveform has become the constant common value. Limit-cycle oscillations are manifested as noise in the filtered digital waveform. Such noise hampers the ability of the system to extract the signal from the filtered digital waveform. The present invention identifies the occurrence of a limit-cycle oscillation as an output different from the common value. The identified limit-cycle oscillation is set equal to the common value.

Abstract: A decimation system comprising a plurality, L, of cascaded Finite Impulse Response (FIR) decimation filters. Each decimation filter has a transfer function of the form H(z)=(1+z−1)N, where N is an integer. Each FIR decimation filter performs decimation by a common factor I. The cascaded FIR decimation filters together achieve a decimation result substantially identical to that of an Nth-order CIC filter (that is, a CIC filter having N integrator stages) that performs decimation by a factor IL.

Abstract: A codifier/decodifier (CODEC) filter circuit (250) connected in a subscriber line interface circuit (202) includes a transmit section (264, 262, 260) for converting differential voltage audio transmit signals representing voice transmissions from the subscriber instrument (202) into encoded digital data for transmission to the digital switching network. A receive section (254, 252) coupled between the digital switching network and subscriber instrument (202) within CODEC (250) for converting encoded digital data representing voice signals switched through the digital switching network to differential voltage audio receive signals for transmission to the subscriber instrument (202). The subscriber loop and subscriber instrument (202) reflect the digital voltage audio signals to the transmit section (264, 262, 260).

Abstract: An IIR filter implementation which provides equivalent results to prior art IIR filters, yet operates about twice as fast as the prior art IIR filters, or requires about half the gate count of the prior art IIR filters and reduced semiconductor area as compared to prior art IIR filters for equivalent speed of operation. An implementation of a high order IIR filter in accordance with one embodiment of the present invention involves the parallel structure of the second-order IIR filters, therefore the filter operates twice as fast as the prior art filter. In accordance with a second embodiment of the invention, low order filters of the same order are reused (used on a time-sharing basis), thereby requiring only a single IIR filter for each order utilized on a time sharing basis, thereby further reducing the number of gates and semiconductor area required.

Abstract: A digital filter having a first plurality of delay components connectable in series and having an input and an output and a second plurality of delay components connectable in series and having an input and said output. A system input is coupled to each of the inputs of the first and second pluralities of delay components. A plurality of adders is provided, each adder couplable alternately to a different delay component of the first plurality of delay components and then to a different delay component of the second plurality of delay components. The number of delay components of the second plurality of delay components is equal in number to the first plurality of delay components. The system input can be concurrently coupled to each of the inputs of the first and second pluralities of delay components. In accordance with a first embodiment of the invention, the number of adders is equal to one less than the number of delay components in first or second pluralities of delay components.