Patents by Inventor Min Su Choi

Min Su Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250031480
    Abstract: An over-soldering prevented tabbing device for manufacturing solar cell modules is disclosed in which the over-soldering is prevented from occurring in the tabbing device for performing the soldering process in manufacturing the solar cell modules. The over-soldering prevented tabbing device according to an embodiment of the present disclosure includes a solar cell module cell that is transported on a conveyor by a unit of cell; a soldering head installed above the solar cell module cell and having a built-in heat source that provides heat to solder the flux coated on the transported solar cell module cell; a driver reciprocating the soldering head in a direction in which the conveyor moves; and a controller controlling the driver.
    Type: Application
    Filed: July 6, 2022
    Publication date: January 23, 2025
    Applicant: HANWHA SOLUTIONS CORPORATION
    Inventors: Min Su LEE, Hyung Do KIM, Jin UK CHOI, Moon Taek LIM, Sung Jin KIM
  • Patent number: 12206420
    Abstract: Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: January 21, 2025
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yi-Gyeong Kim, Young-Su Kwon, Su-Jin Park, Young-Deuk Jeon, Min-Hyung Cho, Jae-Woong Choi
  • Publication number: 20250022716
    Abstract: A method of fabricating a semiconductor device includes providing a substrate, forming a target film, a first mask film, a second mask film, and an upper mask pattern on the substrate, forming a first spacer pattern that includes a first line portion and a second line portion, and a folding portion that connects the first line portion and the second line portion, forming a slit mask pattern that partially covers the first spacer pattern, forming a first mask pattern by patterning the second mask film using the slit mask pattern and the first spacer pattern as an etching mask, forming a second spacer pattern, forming a second mask pattern by patterning the first mask film using the second spacer pattern as an etching mask, and forming a plurality of target patterns by patterning the target film using the second mask pattern as an etching mask.
    Type: Application
    Filed: April 30, 2024
    Publication date: January 16, 2025
    Inventors: Eun Jung KIM, Sung Woo KIM, Hyun Seo SHIN, Min Jeong CHO, Min Su CHOI
  • Publication number: 20240281321
    Abstract: Provided herein may be a memory controller and a memory system including the same. The memory controller may include an error correction circuit configured to perform error correction decoding on data that is read by read retry operations, a buffer memory configured to store decoding history information including retry fail voltages used for a failure in the read retry operations and syndrome weights respectively corresponding to the retry fail voltages, and a processor configured to, when a number of times that the read retry operations fail reaches a threshold number of times, determine a voltage corresponding to a minimum syndrome weight determined based on a relationship between changes in the syndrome weights relative to magnitudes of the retry fail voltages, to be an optimally estimated read voltage, and provide data that is read using the optimally estimated read voltage to the error correction circuit.
    Type: Application
    Filed: August 10, 2023
    Publication date: August 22, 2024
    Inventors: Jae Yong SON, Dae Sung KIM, Min Su CHOI
  • Publication number: 20240283901
    Abstract: A low-latency 360 virtual reality (VR) streaming method for estimating a region of interest (ROI) of a user is proposed. The method may include receiving device pose information from a user device, extracting an ROI of a user, based on the device pose information, and generating ROI tile information corresponding to the ROT. The method may also include generating ROI estimation tile information corresponding to a position at which the ROI is to be changed, and requesting, from a streaming server, a tile corresponding to the ROI tile information and the ROI estimation tile information to receive a high-quality tile stream and a low-quality tile stream of full video that includes a low-quality full video tile stream. The method may further include decoding and rendering the high-quality tile stream and the low-quality full video tile stream and providing the rendered video to the user device.
    Type: Application
    Filed: April 25, 2024
    Publication date: August 22, 2024
    Inventors: Jun Hwan JANG, Woo Chool PARK, Jin Wook YANG, Sang Pil YOON, Min Su CHOI, Jun Suk LEE, Su Ho SONG, Bon Jae KOO
  • Publication number: 20240273844
    Abstract: An augmented reality (AR) streaming device interoperating with an edge server is proposed. The AR streaming device may include a sensing module including a camera and a certain inertia sensor, a display module streaming AR video, a communication module transmitting or receiving data to or from the edge server and the sensing module. The device may also include a memory and a processor executing a program stored in the memory. When image data and inertia data are obtained through the sensing module, the processor may perform synchronization and encoding on the image data and the inertia data to transmit to the edge server through the communication module. When segmentation rendering-processed AR video is received from the edge server, the processor may perform decoding and blending on the segmentation rendering AR video to perform control to be streamed through the display module.
    Type: Application
    Filed: April 25, 2024
    Publication date: August 15, 2024
    Inventors: Jun Hwan JANG, Woo Chool PARK, Jin Wook YANG, Sang Pil YOON, Min Su CHOI, Jun Suk LEE, Su Ho SONG, Bon Jae KOO
  • Patent number: 12050728
    Abstract: A haptic effect transmission method for providing real-time immersive content according to the present invention includes executing participatory content in which one or more users participate, collecting motion information of the users participating in the participatory content through a haptic device, multiplexing the motion information with video and audio files of the participatory content to obtain a multiplexed file, and demultiplexing the multiplexed file and providing the demultiplexed file to a display device and a haptic device of a client terminal.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: July 30, 2024
    Assignee: Korea Electronics Technology Institute
    Inventors: Woo Chool Park, Jun Hwan Jang, Yong Hwa Kim, Jin Wook Yang, Sang Pil Yoon, Hyun Wook Kim, Eun Kyung Cho, Min Su Choi, Jun Suk Lee, Jae Young Yang
  • Publication number: 20240221244
    Abstract: A system and a method for split-rendering for persons with color weakness are proposed. The split-rendering method may include, by a service server, in response to a login of a user device, loading a color weakness profile corresponding to a user of the logging-in user device. The method may also include, by the service server, in response to the user being color-weak in accordance with the loaded color weakness profile, selecting one of a plurality of split-rendering servers. The method may further include, by the service server, transmitting a video content along with the color weakness profile to the selected split-rendering server, and by the service server, transmitting access information about the selected split-rendering server to the user device.
    Type: Application
    Filed: October 31, 2023
    Publication date: July 4, 2024
    Inventors: Jun Hwan JANG, Woo Chool PARK, Min Su CHOI, Jun Suk LEE, Bon Jae KOO
  • Publication number: 20240211345
    Abstract: A memory device may include a read controller and an error correction circuit. The read controller may sequentially perform a plurality of read retry operations on a memory device. The error correction circuit may perform a plurality of first error correction decodings on read data respectively acquired from the plurality of read retry operations, store a plurality of Unsatisfied Syndrome Check (USC) values respectively produced by the plurality of first error correction decodings, and perform a second error correction decoding based on read data corresponding to a minimum USC value among the plurality of USC values.
    Type: Application
    Filed: July 10, 2023
    Publication date: June 27, 2024
    Inventors: Jae Yong SON, Dae Sung KIM, Min Su CHOI
  • Patent number: 11410026
    Abstract: Provided are a neuromorphic circuit having a three-dimensional stack structure and a semiconductor device including the neuromorphic circuit. The semiconductor device includes a first semiconductor layer including one or more synaptic cores, each synaptic core including neural circuits arranged to perform neuromorphic computation. A second semiconductor layer is stacked on the first semiconductor layer and includes an interconnect forming a physical transfer path between synaptic cores. A third semiconductor layer is stacked on the second semiconductor layer and includes one or more synaptic cores. At least one through electrode is formed, through which information is transferred between the first through third semiconductor layers. Information from a first synaptic core in the first semiconductor layer is transferred to a second synaptic core in the third semiconductor layer via the one of more through electrodes and an interconnect of the second semiconductor layer.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: August 9, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woo-Yeong Cho, Seong-Il O, Hak-Soo Yu, Min-Su Choi
  • Publication number: 20220214749
    Abstract: A haptic effect transmission method for providing real-time immersive content according to the present invention includes executing participatory content in which one or more users participate, collecting motion information of the users participating in the participatory content through a haptic device, multiplexing the motion information with video and audio files of the participatory content to obtain a multiplexed file, and demultiplexing the multiplexed file and providing the demultiplexed file to a display device and a haptic device of a client terminal.
    Type: Application
    Filed: September 18, 2019
    Publication date: July 7, 2022
    Inventors: Woo Chool PARK, Jun Hwan JANG, Yong Hwa KIM, Jin Wook YANG, Sang Pil YOON, Hyun Wook KIM, Eun Kyung CHO, Min Su CHOI, Jun Suk LEE, Jae Young YANG
  • Patent number: 11043397
    Abstract: First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: June 22, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myeong-Dong Lee, Min-Su Choi, Jun-Hyeok Ahn, Sung-Hee Han, Ce-Ra Hong
  • Publication number: 20200219732
    Abstract: First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.
    Type: Application
    Filed: July 12, 2019
    Publication date: July 9, 2020
    Inventors: Myeong-Dong LEE, Min-Su CHOI, Jun-Hyeok AHN, Sung-Hee HAN, Ce-Ra HONG
  • Publication number: 20190318230
    Abstract: Provided are a neuromorphic circuit having a three-dimensional stack structure and a semiconductor device including the neuromorphic circuit. The semiconductor device includes a first semiconductor layer including one or more synaptic cores, each synaptic core including neural circuits arranged to perform neuromorphic computation. A second semiconductor layer is stacked on the first semiconductor layer and includes an interconnect forming a physical transfer path between synaptic cores. A third semiconductor layer is stacked on the second semiconductor layer and includes one or more synaptic cores. At least one through electrode is formed, through which information is transferred between the first through third semiconductor layers. Information from a first synaptic core in the first semiconductor layer is transferred to a second synaptic core in the third semiconductor layer via the one of more through electrodes and an interconnect of the second semiconductor layer.
    Type: Application
    Filed: November 15, 2018
    Publication date: October 17, 2019
    Inventors: WOO-YEONG CHO, SEONG-IL O, HAK-SOO YU, MIN-SU CHOI
  • Publication number: 20190214293
    Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a cell region and a peripheral region having different active region densities, forming cell trenches for limiting cell active regions in the cell region so that the cell active regions are formed to be spaced apart by a first width in a first direction and by a second width in a second direction, forming peripheral trenches for limiting a peripheral active region in the peripheral region, and forming, in the cell trenches, a first insulating layer continuously extending in the first and second directions and contacting sidewalls of the cell active regions, and having a thickness equal to or greater than half of the first width and less than half of the second width.
    Type: Application
    Filed: July 6, 2018
    Publication date: July 11, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyu Jin Kim, Min Su Choi, Sung Hee Han, Bong Soo Kim, Yoo Sang Hwang
  • Patent number: 10337391
    Abstract: A device for cooling and heating a urea solution to be injected into exhaust gas discharged from an engine in order to reduce nitrogen oxides in the exhaust gas includes an engine including a cooling fan, a coolant pump, and a main cooler; a urea solution tank storing the urea solution and having an embedded heat exchange pipe through which first coolant and second coolant circulates; an additional coolant tank storing the second coolant; a water pump supplying the second coolant from the additional coolant tank to the heat exchange pipe; a valve configured to be opened or closed in order to supply the first coolant and the second coolant to the heat exchange pipe through a supply line, and to move the first coolant and the second coolant, which are discharged from the heat exchange pipe through a discharge line, to rise coolant pump and the additional coolant tank, respectively and a controller for supplying the second coolant to the heat exchange pipe through the supply line when the urea solution temperatu
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: July 2, 2019
    Assignee: Volvo Construction Equipment AB
    Inventors: Dong-Myoung Choi, Yu-Hee Lee, Eun-Geon Yuk, Sung-Hwan Shin, Min-Su Choi
  • Patent number: 10199379
    Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Hee Cho, Woo Song Ahn, Min Su Choi, Satoru Yamada, Jun Soo Kim, Sung Sam Lee
  • Publication number: 20180209325
    Abstract: A device for cooling and heating a urea solution to be injected into exhaust gas discharged from an engine in order to reduce nitrogen oxides in the exhaust gas includes an engine including a cooling fan, a coolant pump, and a main cooler; a urea solution tank storing the urea solution and having an embedded heat exchange pipe through which first coolant and second coolant circulates; an additional coolant tank storing the second coolant; a water pump supplying the second coolant from the additional coolant tank to the heat exchange pipe; a valve configured to be opened or closed in order to supply the first coolant and the second coolant to the heat exchange pipe through a supply line, and to move the first coolant and the second coolant, which are discharged from the heat exchange pipe through a discharge line, to rise coolant pump and the additional coolant tank, respectively and a controller for supplying the second coolant to the heat exchange pipe through the supply line when the urea solution temperatu
    Type: Application
    Filed: July 29, 2015
    Publication date: July 26, 2018
    Applicant: VOLVO CONSTRUCTION EQUIPMENT AB
    Inventors: Dong-Myoung CHOI, Yu-Hee LEE, Eun-Geon YUK, Sung-Hwan SHIN, Min-Su CHOI
  • Publication number: 20180108662
    Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.
    Type: Application
    Filed: December 7, 2017
    Publication date: April 19, 2018
    Inventors: Min Hee Cho, Woo Song Ahn, Min Su Choi, Satoru Yamada, Jun Soo Kim, Sung Sam Lee
  • Patent number: 9853031
    Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: December 26, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Hee Cho, Woo Song Ahn, Min Su Choi, Satoru Yamada, Jun Soo Kim, Sung Sam Lee