Abstract: Provided are an electrode assembly, a battery, and a battery pack and vehicle including the same. An electrode assembly, in which a first electrode, a second electrode, and a separator interposed therebetween are wound about an axis to define a core and an outer circumferential surface. At least one of the first electrode and the second electrode includes, at a long side end portion, an uncoated portion exposed beyond the separator in a direction of the axis. At least a part of the uncoated portion is bent in a radial direction of the electrode assembly to define a bent surface region having overlapping layers of the uncoated portion. The bent surface region includes a welding target region having a number of the overlapping layers of the uncoated portion, and the welding target region extends along a radial direction of the electrode assembly.

Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on an axis to define a core and an outer circumference. The first electrode includes an uncoated portion at a long side end thereof and exposed out of the separator along a winding axis direction of the electrode assembly. A part of the uncoated portion is bent in a radial direction of the electrode assembly to form a bending surface region that includes overlapping layers of the uncoated portion, and in a partial region of the bending surface region, the number of stacked layers of the uncoated portion is 10 or more in the winding axis direction of the electrode assembly.

Abstract: A method of a first terminal may include: identifying first RB set(s) to be used for SL communication among consecutive RB sets through an LBT procedure; identifying a first subchannel group included in the first RB set(s) and a second subchannel group including a first PRB in the first RB set(s), the first PRB being not included in the first subchannel group; configuring the first PRB within the second subchannel group as an SL communication resource; and transmitting, to a second terminal, control information indicating that the first PRB is configured as the SL communication resource.

Abstract: Provided are a neuromorphic circuit having a three-dimensional stack structure and a semiconductor device including the neuromorphic circuit. The semiconductor device includes a first semiconductor layer including one or more synaptic cores, each synaptic core including neural circuits arranged to perform neuromorphic computation. A second semiconductor layer is stacked on the first semiconductor layer and includes an interconnect forming a physical transfer path between synaptic cores. A third semiconductor layer is stacked on the second semiconductor layer and includes one or more synaptic cores. At least one through electrode is formed, through which information is transferred between the first through third semiconductor layers. Information from a first synaptic core in the first semiconductor layer is transferred to a second synaptic core in the third semiconductor layer via the one of more through electrodes and an interconnect of the second semiconductor layer.

Abstract: A haptic effect transmission method for providing real-time immersive content according to the present invention includes executing participatory content in which one or more users participate, collecting motion information of the users participating in the participatory content through a haptic device, multiplexing the motion information with video and audio files of the participatory content to obtain a multiplexed file, and demultiplexing the multiplexed file and providing the demultiplexed file to a display device and a haptic device of a client terminal.

Abstract: First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.

Abstract: First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.

Abstract: Provided are a neuromorphic circuit having a three-dimensional stack structure and a semiconductor device including the neuromorphic circuit. The semiconductor device includes a first semiconductor layer including one or more synaptic cores, each synaptic core including neural circuits arranged to perform neuromorphic computation. A second semiconductor layer is stacked on the first semiconductor layer and includes an interconnect forming a physical transfer path between synaptic cores. A third semiconductor layer is stacked on the second semiconductor layer and includes one or more synaptic cores. At least one through electrode is formed, through which information is transferred between the first through third semiconductor layers. Information from a first synaptic core in the first semiconductor layer is transferred to a second synaptic core in the third semiconductor layer via the one of more through electrodes and an interconnect of the second semiconductor layer.

Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a cell region and a peripheral region having different active region densities, forming cell trenches for limiting cell active regions in the cell region so that the cell active regions are formed to be spaced apart by a first width in a first direction and by a second width in a second direction, forming peripheral trenches for limiting a peripheral active region in the peripheral region, and forming, in the cell trenches, a first insulating layer continuously extending in the first and second directions and contacting sidewalls of the cell active regions, and having a thickness equal to or greater than half of the first width and less than half of the second width.

Abstract: A device for cooling and heating a urea solution to be injected into exhaust gas discharged from an engine in order to reduce nitrogen oxides in the exhaust gas includes an engine including a cooling fan, a coolant pump, and a main cooler; a urea solution tank storing the urea solution and having an embedded heat exchange pipe through which first coolant and second coolant circulates; an additional coolant tank storing the second coolant; a water pump supplying the second coolant from the additional coolant tank to the heat exchange pipe; a valve configured to be opened or closed in order to supply the first coolant and the second coolant to the heat exchange pipe through a supply line, and to move the first coolant and the second coolant, which are discharged from the heat exchange pipe through a discharge line, to rise coolant pump and the additional coolant tank, respectively and a controller for supplying the second coolant to the heat exchange pipe through the supply line when the urea solution temperatu

Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.

Abstract: A device for cooling and heating a urea solution to be injected into exhaust gas discharged from an engine in order to reduce nitrogen oxides in the exhaust gas includes an engine including a cooling fan, a coolant pump, and a main cooler; a urea solution tank storing the urea solution and having an embedded heat exchange pipe through which first coolant and second coolant circulates; an additional coolant tank storing the second coolant; a water pump supplying the second coolant from the additional coolant tank to the heat exchange pipe; a valve configured to be opened or closed in order to supply the first coolant and the second coolant to the heat exchange pipe through a supply line, and to move the first coolant and the second coolant, which are discharged from the heat exchange pipe through a discharge line, to rise coolant pump and the additional coolant tank, respectively and a controller for supplying the second coolant to the heat exchange pipe through the supply line when the urea solution temperatu

Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.

Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.

Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.

Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.

Abstract: Disclosed herein is a method of coating a brake hose fitting. The method includes plating a brake hose fitting with a zinc-nickel (Zn—Ni) alloy including about 6˜12 wt % of nickel (Ni). The method further includes post-treating the plated brake hose fitting with a silicon (Si) solution.