Abstract: A method and apparatus for encoding point cloud data and a method for transmitting data generated by the point cloud data encoding method are provided. A method of encoding point cloud data may comprise obtaining the point cloud data, quantizing vertices of meshes within the obtained point cloud data, and generating final meshes based on the quantized vertices.

Abstract: A multi-subscriber identification module (SIM) device is provided, and includes first and second SIMs, first and second radio frequency (RF) resources, and a baseband processor. The first and second SIMs are for using first and second services of first and second networks respectively. The first RF resource supports a non-limiting channel configuration use in accordance with a radio resource control (RRC) protocol. The second RF resource supports a limiting channel configuration use in accordance with the RRC protocol. The baseband processor, in a dual radio (DR) mode, configures one of the first and second SIMs as a main SIM based on information on the first and second networks, allots the first RF resource to the main SIM, configures the other one as a sub-SIM, and allots the second RF resource to the sub-SIM.

Abstract: A memory system includes a control device suitable for generating first command signals for a unit time and storing first count information corresponding to the number of times to generate the first command signals based on temperature information, in a training mode, and generating second command signals based on the first count information and second count information in a normal mode, the second count information corresponding to the number of times to generate the second command signals for the unit time, and a memory device suitable for performing an internal operation based on the first command signals and providing the control device with the temperature information when performing the internal operation, in the training mode, and performing an internal operation based on the second command signals in the normal mode.

Abstract: A memory system includes a control device suitable for generating first command signals for a unit time and storing first count information corresponding to the number of times to generate the first command signals based on temperature information, in a training mode, and generating second command signals based on the first count information and second count information in a normal mode, the second count information corresponding to the number of times to generate the second command signals for the unit time, and a memory device suitable for performing an internal operation based on the first command signals and providing the control device with the temperature information when performing the internal operation, in the training mode, and performing an internal operation based on the second command signals in the normal mode.

Abstract: A semiconductor package includes a semiconductor chip including at least one vertical hole that penetrates therethrough in a vertical direction, and a mold covering the semiconductor chip, and including at least one first horizontal hole and at least one second horizontal hole that are formed in a horizontal direction, wherein the first horizontal hole and the second horizontal hole are connected through the vertical hole.

Abstract: A multi-subscriber identification module (SIM) device is provided, and includes first and second SIMs, first and second radio frequency (RF) resources, and a baseband processor. The first and second SIMs are for using first and second services of first and second networks respectively. The first RF resource supports a non-limiting channel configuration use in accordance with a radio resource control (RRC) protocol. The second RF resource supports a limiting channel configuration use in accordance with the RRC protocol. The baseband processor, in a dual radio (DR) mode, configures one of the first and second SIMs as a main SIM based on information on the first and second networks, allots the first RF resource to the main SIM, configures the other one as a sub-SIM, and allots the second RF resource to the sub-SIM.

Abstract: In an information processing method performed in a first gateway device among a plurality of gateway devices for managing a plurality of nodes, a current characteristic value recorded in a first node of the plurality of nodes is replaced with a new characteristic value. Then, a database is updated so that the database stores new information on the first node to which the new characteristic value is reflected. The new information on the first node is transmitted to another gateway device of the plurality of gateway devices.

Abstract: A composition for forming an electrode includes a conductive powder, a glass frit, an organic vehicle, and a burn-out retardant. The burn-out retardant exhibits a residual carbon of greater than or equal to about 1 wt % at a temperature of about 600° C. based on the initial amount of 100 wt % and an exothermic peak at about 200° C. to about 500° C.

Abstract: A memory device may include a plurality of memory cells; a refresh counter suitable for generating a refresh address; an address storage circuit suitable for storing an additional refresh address; an error detection unit suitable for detecting an error of selected memory cells of the plurality of memory cells in response to a refresh command in a detection period; and a refresh control unit suitable for refreshing memory cells corresponding to the refresh address or the additional refresh address among the memory cells in response to the refresh command, and controlling the refreshing of the memory cells to be delayed in the detection period.

Abstract: A memory device may include a plurality of memory cells; an error detection unit suitable for: latching data read a first time from at least one selected memory cell of the plurality of memory cells in a detection period, comparing data read a second time from the at least one selected memory cell with the latched data, and detecting an error of the at least one selected memory cell in the detection when the date read a second time from the at least one substantially the same with the latched data.

Abstract: A memory device may include a plurality of memory cells; and an error detection unit suitable for latching first read data of one or more memory cells selected from the plurality of memory cells after refreshing the selected memory cells, in a first phase, and suitable for detecting errors of the selected memory cells before refreshing the selected memory cells, in a second phase.

Abstract: A composition for forming an electrode includes a conductive powder, a glass frit, an organic vehicle, and a burn-out retardant. The burn-out retardant exhibits a residual carbon of greater than or equal to about 1 wt % at a temperature of about 600° C. based on the initial amount of 100 wt % and an exothermic peak at about 200° C. to about 500° C.

Abstract: A memory device may include a plurality of memory cells; an error detection unit suitable for: latching data read a first time from at least one selected memory cell of the plurality of memory cells in a detection period, comparing data read a second time from the at least one selected memory cell with the latched data, and detecting an error of the at least one selected memory cell in the detection when the date read a second time from the at least one substantially the same with the latched data.

Abstract: A memory device may include a plurality of memory cells; and an error detection unit suitable for latching first read data of one or more memory cells selected from the plurality of memory cells after refreshing the selected memory cells, in a first phase, and suitable for detecting errors of the selected memory cells before refreshing the selected memory cells, in a second phase.

Abstract: A memory device may include a plurality of memory cells; a refresh counter suitable for generating a refresh address; an address storage circuit suitable for storing an additional refresh address; an error detection unit suitable for detecting an error of selected memory cells of the plurality of memory cells in response to a refresh command in a detection period; and a refresh control unit suitable for refreshing memory cells corresponding to the refresh address or the additional refresh address among the memory cells in response to the refresh command, and controlling the refreshing of the memory cells to be delayed in the detection period.

Abstract: A semiconductor memory device includes: a master chip suitable for generating a plurality of first control signals and a second control signal based on a read command; and a plurality of slave chips each suitable for latching data read from a plurality of memory cells included in a corresponding slave chip and transmitting the latched data to the master chip based on a correspond control signal of the first control signals, wherein the master chip latches the data transmitted from the slave chips based on the first control signals and outputs the data latched in the master chip based on the second control signal.

Abstract: A semiconductor memory device includes: a master chip suitable for generating a plurality of first control signals and a second control signal based on a read command; and a plurality of slave chips each suitable for latching data read from a plurality of memory cells included in a corresponding slave chip and transmitting the latched data to the master chip based on a correspond control signal of the first control signals, wherein the master chip latches the data transmitted from the slave chips based on the first control signals and outputs the data latched in the master chip based on the second control signal.

Abstract: A delay locked loop (DLL) circuit includes a timing pulse generating unit configured to generate a plurality of timing pulses, which are sequentially pulsed during delay shifting update periods, in response to a source clock, wherein the number of the generated timing pulses changes according to a frequency of the source clock; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay replica modeling unit configured to reflect actual delay conditions of the internal clock path on an output clock of the clock delay unit, and to output the feedback clock.

Abstract: A latency control circuit of a semiconductor device includes a phase detection unit configured to generate phase information regarding a phase difference between an external clock and an internal clock, a delay amount deciding unit configured to decide a latency delay amount based on path information of an input signal, a latency value of the input signal, and the phase information, and a latency delay unit configured to generate a latency signal by delaying the input signal according to the latency delay amount and the phase information to produce a delayed input signal and by synchronizing the delayed input signal with the internal clock.

Abstract: A latency control circuit of a semiconductor device includes a phase detection unit configured to generate phase information regarding a phase difference between an external clock and an internal clock, a delay amount deciding unit configured to decide a latency delay amount based on path information of an input signal, a latency value of the input signal, and the phase information, and a latency delay unit configured to generate a latency signal by delaying the input signal according to the latency delay amount and the phase information to produce a delayed input signal and by synchronizing the delayed input signal with the internal clock.