Abstract: A semiconductor system includes a semiconductor device and a controller. The semiconductor device includes a first memory rank and is configured to perform, in response to receiving a first write command, a first write operation of writing first data to the first memory rank. The semiconductor device includes a second memory rank and is configured to perform, in response to receiving a second write command, a second write operation of writing second data to the second memory rank. The controller is configured to receive at least one write request and responsively generate the first and second write commands separated in time so that a transition time interval between generation of the first write command and generation of the second write command is based on the second memory rank being different from the first memory rank and based on a comparison of a write preamble period to a write post-amble period.

Abstract: A semiconductor device includes an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit is configured to generate an internal command pulse based on a write signal, a latency code, and an offset code. The sense data generation circuit is configured to generate a sense data based on the internal command pulse and an internal data strobe signal and configured to generate the sense data based on the internal command pulse and a delayed strobe signal.

Abstract: A semiconductor package of a pin-grid-array type includes a bump pad on a first substrate, a metal socket on a second substrate, a core material for reverse reflow on the bump pad, and solder paste or a solder bump forming a solder layer on the core material for reverse reflow. The solder paste or the solder bump is in contact with the bump pad. The core material for reverse reflow and the solder paste or the solder bump bonded to the core material for reverse reflow are used as a pin and detachably attached to the metal socket. The core material for reverse reflow includes a core, a first metal layer directly coated on the core, and a second metal layer directly coated on the first metal layer.

Abstract: Provided is a semiconductor package including a first bump pad on a first substrate, a second bump pad on a second substrate, a core material for reverse reflow between the first bump pad and the second bump pad, and a solder member forming a solder layer on the core material for reverse reflow. The solder member is in contact with the first bump pad and the second bump pad. Each of a first diameter of the first bump pad and a second diameter of the second bump pad is at least about 1.1 times greater than a third diameter of the core material for reverse reflow. The core material for reverse reflow includes a core, a first metal layer directly coated on the core, and a second metal layer directly coated on the first metal layer.

Abstract: A system for performing a phase matching operation includes a controller configured to output a clock, a command, and a strobe signal, and to input/output data. The system also includes a semiconductor device configured to generate an internal strobe signal by matching the phases of the command and the strobe signal according to the clock, and to input/output the data in synchronization with the internal strobe signal, wherein the semiconductor device generates the internal strobe signal from the strobe signal by compensating for a delay amount of a first path to which the command is inputted and a delay amount of a second path to which the strobe signal is inputted.

Abstract: A system for performing a phase matching operation includes a controller configured to output a dock, a command, and a strobe signal, and to input/output data. The system also includes a semiconductor device configured to generate an internal strobe signal by matching the phases of the command and the strobe signal according to the clock, and to input/output the data in synchronization with the internal strobe signal, wherein the semiconductor device generates the internal strobe signal from the strobe signal by compensating for a delay amount of a first path to which the command is inputted and a delay amount of a second path to which the strobe signal is inputted.

Abstract: A memory may include multiple rows each coupled to multiple memory cells; a target row classification circuit suitable for classifying, as a target row, a row, among the multiple rows, that is susceptible to data loss as a result of activity of an adjacent row; and a target row signal generation circuit suitable for sequentially activating a target row active signal for activating the target row and a target row precharge signal for precharging the target row in response to a precharge command.

Abstract: The optical film according to the present invention has a feature that it has excellent property of blocking UV light and exhibits high slip property and thus enables self-winding even while using an acrylic resin not containing monomers having a ring structure.

Abstract: The optical film according to the present invention has a feature that it has high adhesiveness and excellent property of blocking UV light even while using an acrylic resin having no ring structure in the main chain.

Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a fine training circuit configured to generate a fine result signal based on a clock signal, a data strobe signal, and a command. The semiconductor apparatus may include a coarse training circuit configured to generate a coarse result signal based on the clock signal, the data strobe signal, and the command and to set an offset of a write enable signal based on an offset control signal.

Abstract: The optical film according to the present invention has a feature that it can implement zero retardation and have high slip property and thus enabling self-winding, even while using an acrylic resin not containing monomers having a ring structure.

Abstract: A method includes performing a first write leveling training operation and performing a second write leveling training operation. The first write leveling training operation is performed to generate transmission data based on a data strobe signal and an internal command pulse and to generate a latency code. The second write leveling training operation is performed to generate the transmission data based on the data strobe signal and the internal command pulse.

Abstract: A multi-subscriber identification module (SIM) device is provided, and includes first and second SIMs, first and second radio frequency (RF) resources, and a baseband processor. The first and second SIMs are for using first and second services of first and second networks respectively. The first RF resource supports a non-limiting channel configuration use in accordance with a radio resource control (RRC) protocol. The second RF resource supports a limiting channel configuration use in accordance with the RRC protocol. The baseband processor, in a dual radio (DR) mode, configures one of the first and second SIMs as a main SIM based on information on the first and second networks, allots the first RF resource to the main SIM, configures the other one as a sub-SIM, and allots the second RF resource to the sub-SIM.

Abstract: A memory system includes a control device suitable for generating first command signals for a unit time and storing first count information corresponding to the number of times to generate the first command signals based on temperature information, in a training mode, and generating second command signals based on the first count information and second count information in a normal mode, the second count information corresponding to the number of times to generate the second command signals for the unit time, and a memory device suitable for performing an internal operation based on the first command signals and providing the control device with the temperature information when performing the internal operation, in the training mode, and performing an internal operation based on the second command signals in the normal mode.

Abstract: A memory system includes a control device suitable for generating first command signals for a unit time and storing first count information corresponding to the number of times to generate the first command signals based on temperature information, in a training mode, and generating second command signals based on the first count information and second count information in a normal mode, the second count information corresponding to the number of times to generate the second command signals for the unit time, and a memory device suitable for performing an internal operation based on the first command signals and providing the control device with the temperature information when performing the internal operation, in the training mode, and performing an internal operation based on the second command signals in the normal mode.

Abstract: A semiconductor system includes a semiconductor device and a controller. The semiconductor device includes a first memory rank and is configured to perform, in response to receiving a first write command, a first write operation of writing first data to the first memory rank. The semiconductor device includes a second memory rank and is configured to perform, in response to receiving a second write command, a second write operation of writing second data to the second memory rank. The controller is configured to receive at least one write request and responsively generate the first and second write commands separated in time so that a transition time interval between generation of the first write command and generation of the second write command is based on the second memory rank being different from the first memory rank and based on a comparison of a write preamble period to a write post-amble period.

Abstract: A semiconductor device may include an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit may generate an internal command pulse from a write signal based on an offset code and an internal clock signal. The sense data generation circuit may generate sense data from an internal data strobe signal based on the internal command pulse. The internal command pulse may be generated by delaying the write signal by a shift period based on the internal clock signal. The shift period may be controlled by the offset code.

Abstract: A semiconductor device may include an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit may generate an internal command pulse from a write signal based on an offset code and an internal clock signal. The sense data generation circuit may generate sense data from an internal data strobe signal based on the internal command pulse. The internal command pulse may be generated by delaying the write signal by a shift period based on the internal clock signal. The shift period may be controlled by the offset code.

Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes an error detection circuit. The second semiconductor device is stacked with the first semiconductor device and is electrically connected to the first semiconductor device via a first through electrode and a second through electrode. The first and second semiconductor devices are configured to receive or output first data and second data via the second through electrode according to an operation mode and are configured to detect errors of the first data and the second data using the error detection circuit.

Abstract: A semiconductor package includes a semiconductor chip including at least one vertical hole that penetrates therethrough in a vertical direction, and a mold covering the semiconductor chip, and including at least one first horizontal hole and at least one second horizontal hole that are formed in a horizontal direction, wherein the first horizontal hole and the second horizontal hole are connected through the vertical hole.