Abstract: Methods, apparatuses and articles for testing security of a mapping function—such as a Physically Unclonable Function (PUF)—of an integrated circuit (IC) are disclosed. In various embodiments, one or more tests may be performed. In various embodiments, the tests may include a predictability test, a collision test, a sensitivity test, a reverse-engineering test and an emulation test. In various embodiments, a test may determine a metric to indicate a level of security or vulnerability. In various embodiments, a test may include characterizing one or more delay elements and/or path segments of the mapping function. Other embodiments may be described and claimed.

Abstract: Techniques are generally described for determining locations of a plurality of communication devices in a network. In some examples, methods for determining locations of a plurality of communication devices in a network may comprises formulating the determination as a quantitative problem based at least in part on one or more attributes between individual communication devices and one or more beacon nodes whose locations are known, wherein the quantitative problem is expressed in terms of an objective function, one or more constraints, and one or more models, and solving the quantitative problem to determine the location of at least a portion of the one or more communication devices, wherein the solving includes manipulation of at least the objective function, one of the one or more constraints or one of the one or more models. Additional variants and embodiments are also disclosed.

Abstract: Techniques are generally described for non-invasive, post-silicon characterization of—leakage power for devices of an integrated circuit (IC). A system of sparse leakage power equations may be developed for the devices (e.g. gates) within the IC to be solved using compressive sensing (CS) techniques. Input Vectors (IV) may be applied at input terminal of the IC, and power of the IC may be measured. The measurements may be used in conjunction with the set of sparse equations to determine leakage power values for individual devices, not directly accessible. Pre-processing and post-processing techniques may be employed to make the system of equations more sparse and further improve the efficiency of applying CS techniques to solve the equations. Example processing may include variable splitting, device grouping, IV and equation selection, measurement under elevated IC temperature, and bootstrapping. Other aspects may be disclosed and claimed.

Abstract: Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined.

Abstract: The present disclosure generally relates to methods for improving wireless communications. Example embodiments include placing a wireless communication obstacle at an optimal or approximately optimal position to improve one or more characteristics of a wireless communication link between two wireless communication devices. The wireless communication obstacle may be adapted to absorb or reflect one or more wireless communications from other wireless communication devices to prevent and/or reduce interference with the wireless communication link between the two wireless communication devices.

Abstract: Techniques are generally described for addressing computation errors via coordinated computation on two computing platforms are disclosed. In some embodiments, one or more cuts may be taken of a computation to observe variables, and the observations may be analyzed to detect errors. Corrections may be created for the detected errors. The disclosed techniques may be employed in power and/or energy minimization/reduction, and debugging, among other goals. Other embodiments may be disclosed and/or claimed.

Abstract: Techniques are generally disclosed for using an operating entity, including a method, apparatus, and/or system to control usage of the operating entity. In various embodiments, an in-use signal generator may be configured to generate at least one in-use signal, with the at least one in-use signal having a signal duration representative of at least one usage episode of the operating entity. An aging circuit may be coupled to the in-use signal generator and configured to output at least one age-affected signal in response to the at least one in-use signal. A metering module may be coupled to the aging circuit and, in response to the at least one age-affected signal, and configured to measure a signal characteristic of the at least one age-affected signal and translate the signal characteristic into a generated quantity of accumulative usage of the aging circuit.

Abstract: Technology for semantic compression is disclosed. In various embodiments, the technology receives data that represents one or more physical attributes sensed by one or more sensors; employs at least one pattern or statistical feature to identify a first region and a second region in the received data; computes a first utility and a first relevant feature for the first region, and a second utility and a second relevant feature for the second region; and identifies based on at least the first utility and the second utility a first compression method to apply to the first region and a second compression method to apply to the second region wherein the first and the second compression methods have different compression rates, different feature preservation characteristics, or both.

Abstract: Technology for adaptive compression is described (“the technology”). The technology may identify two or more partitions of a data stream; optionally pre-process data in each partition; create one or more evaluation functions to evaluate a suitability for compression of the data in each partition using a set of potential compression methods; process the created one or more evaluation functions; choose a subset of the set of potential compression methods for each segment at least partly by analyzing the evaluation functions; select a compression method for each segment based on a compression ratio of compressing the sequence of used compression methods and a compression rate of the data; compress the data in each partition using the selected compression method for the partition; compress a subsequence that indicates which compression method is used for each segment.

Abstract: Techniques are generally described for non-invasive, post-silicon characterization of—leakage power for devices of an integrated circuit (IC). A system of sparse leakage power equations may be developed for the devices (e.g. gates) within the IC to be solved using compressive sensing (CS) techniques. Input Vectors (IV) may be applied at input terminal of the IC, and power of the IC may be measured. The measurements may be used in conjunction with the set of sparse equations to determine leakage power values for individual devices, not directly accessible. Pre-processing and post-processing techniques may be employed to make the system of equations more sparse and further improve the efficiency of applying CS techniques to solve the equation. Example processing may include variable splitting, device grouping, IV and equation selection, measurement under elevated IC temperature, and bootstrapping. Other aspects may be disclosed and claimed.

Abstract: Techniques are generally disclosed for using an operating entity, including a method, apparatus, and/or system to control usage of the operating entity. In various embodiments, an in-use signal generator may be configured to generate at least one in-use signal, with the at least one in-use signal having a signal duration representative of at least one usage episode of the operating entity. An aging circuit may be coupled to the in-use signal generator and configured to output at least one age-affected signal in response to the at least one in-use signal. A metering module may be coupled to the aging circuit and, in response to the at least one age-affected signal, and configured to measure a signal characteristic of the at least one age-affected signal and translate the signal characteristic into a generated quantity of accumulative usage of the aging circuit.

Abstract: Techniques are generally described for addressing computation errors via coordinated computation on two computing platforms are disclosed. In some embodiments, one or more cuts may be taken of a computation to observe variables, and the observations may be analyzed to detect errors. Corrections may be created for the detected errors. The disclosed techniques may be employed in power and/or energy minimization/reduction, and debugging, among other goals. Other embodiments may be disclosed and/or claimed.

Abstract: Techniques for non-invasive, post-silicon characterization of signal propagation delay/timing of devices in an integrated circuit (IC) are generally disclosed. A system of equations may be developed based on a plurality of sensitizable signal paths (SSPs) of the IC for characterizing signal propagation delay or timing of devices within the SSPs. Input Vectors (IVs) may be selected and consecutively applied at one or more input sequential element devices of the IC associated with the SSPs with to produce corresponding output values at one or more output sequential element devices of the IC associated with the SSPs. Various pre-processing and post-processing techniques may be practiced to further improve accuracy of solution of the equations to enable efficient determination of solutions. Example techniques may include variable splitting, device clustering, IV and equation selection, and boosting, among others. Other aspects may also be disclosed and claimed.

Abstract: Embodiments provide methods and apparatuses for detecting errors in a computation using state variables. In various embodiments, corrections of the errors through the state variables are also provided. In various embodiments, the disclosed techniques may be used for power and/or energy minimization/reduction, and debugging, among other goals. Other embodiments and/or applications may be disclosed and/or claimed.

Abstract: A method and apparatus for system level management to a wireless device using measurements. In various embodiments, a system level manager independent of the operating system of a wireless device may be configured to determine relevant metrics to obtain measurements, based at least in part on the quality of service needs and performance/resource consumption models of the wireless device. In various embodiments, the system level manager may be further configured to determine management actions to be taken by the operating system based at least in part on the measurements obtained.

Abstract: Technologies are described herein for intentionally allowing errors in a computational system to optimize energy consumption of the computational system. A cost-benefit analysis is performed to identify one or more allowable errors and one or more non-allowable errors in the computational system. The allowable errors may be identified by the cost-benefit analysis as being acceptable errors for optimizing energy consumption with respect to accuracy of the computational system. The non-allowable errors may be identified by the cost-benefit analysis as being unacceptable errors for optimizing energy consumption with respect to accuracy of the computational system. The computational system is transformed from a first state in which the computational system corrects or prevents the allowable errors and the non-allowable errors into a second state in which the computational system allows the allowable errors and corrects or prevents the non-allowable errors.

Abstract: Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.

Abstract: Techniques are generally described for determining locations of a number of communication devices in a network. A method for determining locations of a number of communication devices in a network may include one or more of solving an objective function to determine a first set of locations of one or more of the number of communication devices. The method may further include re-solving either the objective function or a modified variant of the objective function, to determine a second set of locations of the communication devices; comparing the first set of locations with the second set of locations; and determining the locations of the communication devices based at least in part on the comparing.

Abstract: Techniques are generally described for correcting computation errors via input compensation and/or input overcompensation. In various examples, errors of a computation may be detected, and input compensation and/or overcompensation to correct the errors may be created. The disclosed techniques may be used for power and/or energy minimization/reduction, and debugging, among other applications. Other embodiments and/or applications may be disclosed and/or claimed.

Abstract: Data compression technology (“the technology”) is disclosed that can employ two or more prediction models contemporaneously. The technology receives data from one or more sources; shifts or re-sample one of more corresponding signals; creates a prediction model of uncompressed samples using at least two different individual or composite models; selects a subset of the models for prediction of samples; determines an order in which signals will be compressed; formulates a combined predictions model using the selected subset of models; predicts a future value for the data using the combined compression model; defines a function that has as parameters at least the predicted future values for the data and actual values; selects a compression method for the values of the function; and compresses the data using at least the predicted value of the function.