Abstract: Differential uncloneable variability-based cryptography techniques are provided. The differential cryptography includes a hardware based public physically uncloneable function (PPUF) to perform the cryptography. The PPUF includes a first physically uncloneable function (PUF) and a second physically uncloneable function. An arbiter determines the output of the circuit using the outputs of the first and second PUFs. Cryptography can be performed by simulating the PPUF with selected input. The output of the simulation, along with timing information about a set of inputs from where the corresponding input is randomly selected for simulation, is used by the communicating party that has the integrated circuit with the PPUF to search for an input that produces the output. The input can be configured to be the secret key or a part of the secret key.

Abstract: Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined.

Abstract: Technologies are described herein related to multi-core processors that are adapted to share processor resources. An example multi-core processor can include a plurality of processor cores. The multi-core processor further can include a shared register file selectively coupled to two or more of the plurality of processor cores, where the shared register file is adapted to serve as a shared resource among the selected processor cores.

Abstract: Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.

Abstract: Methods, apparatuses and articles for testing security of a mapping function—such as a Physically Unclonable Function (PUF)—of an integrated circuit (IC) are disclosed. In various embodiments, one or more tests may be performed. In various embodiments, the tests may include a predictability test, a collision test, a sensitivity test, a reverse-engineering test and an emulation test. In various embodiments, a test may determine a metric to indicate a level of security or vulnerability. In various embodiments, a test may include characterizing one or more delay elements and/or path segments of the mapping function. Other embodiments may be described and claimed.

Abstract: Techniques are generally described for transitioning a Finite State Machine (FSM) of an integrated circuit from a first state to a second state or a replicated variant of the second state in lieu of the second state, and out of the replicated variant of the second state, using a robust physically unclonable function (PUF), an event generator and a control block of the IC. In various embodiments, the techniques leverage on manufacturing variability of the IC. In various embodiments, the techniques are employed to control activation or deactivation of the IC. Other embodiments may be disclosed and claimed.

Abstract: Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.

Abstract: Techniques for non-invasive, post-silicon characterization of signal propagation delay/timing of devices in an integrated circuit (IC) are generally disclosed. A system of equations may be developed based on a plurality of sensitizable signal paths (SSPs) of the IC for characterizing signal propagation delay or timing of devices within the SSPs. Input Vectors (IVs) may be selected and consecutively applied at one or more input sequential element devices of the IC associated with the SSPs with to produce corresponding output values at one or more output sequential element devices of the IC associated with the SSPs. Various pre-processing and post-processing techniques may be practiced to further improve accuracy of solution of the equations to enable efficient determination of solutions. Example techniques may include variable splitting, device clustering, IV and equation selection, and boosting, among others. Other aspects may also be disclosed and claimed.

Abstract: Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.

Abstract: A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the solution space through a software simulation, (C) evaluating the instances through a hardware simulation, and (D) updating the instances in response to the software simulation and the hardware simulation to approach an optimum instance of the instances for the circuit.

Abstract: Techniques related to a localized routing approach are generally described where the number of transmissions, the maximum number of transmission per node, effective bandwidth, the latency, overall energy consumption, the maximum energy consumption, or other individual or composite objective in a wireless network may be optimized. The localized routing approach may use a metric that combines immediate progress benefit and expense with a statistics-based forward looking estimation of future routing properties and cost. The protocol may also employ a combination of probabilistic and deterministic mechanism to detect and escape local minima.

Abstract: The present disclosure generally relates to techniques to reduce energy consumption in a multiple-input multiple-output (MIMO) system. Some example embodiments may include collecting a set of information associated with one or more of an energy consumption, a network traffic condition, an environmental condition, and/or quality of a communication link associated with the first wireless communication device and/or the MIMO system, configuring the first wireless communication device to operate at a first reduced energy consumption level based on the collected set of information, identifying operation information associated with the first wireless communication device based upon at least the configuration of the first wireless communication device, and transmitting the operation information for reception by the second wireless communication device so that the second wireless communication device can be configured to operate at a second reduced energy consumption level based on the operation information.

Abstract: Techniques are generally described related to model an actual sports game in a cyber-physical game. One example method may include one or more of receiving a first set of data collected from the actual sports game as the actual sports game is being played, generating an objective in the cyber-physical game based on the first set of data, receiving a second set of data as the cyber-physical game is being played, and evaluating the second set of data in view of the objective to generate a score and to determine whether to continue the cyber-physical game as the actual sports game is being played.

Abstract: Techniques are generally described for non-invasive, post-silicon characterization of—leakage power for devices of an integrated circuit (IC). A system of sparse leakage power equations may be developed for the devices (e.g. gates) within the IC to be solved using compressive sensing (CS) techniques. Input Vectors (IV) may be applied at input terminal of the IC, and power of the IC may be measured. The measurements may be used in conjunction with the set of sparse equations to determine leakage power values for individual devices, not directly accessible. Pre-processing and post-processing techniques may be employed to make the system of equations more sparse and further improve the efficiency of applying CS techniques to solve the equation. Example processing may include variable splitting, device grouping, IV and equation selection, measurement under elevated IC temperature, and bootstrapping. Other aspects may be disclosed and claimed.

Abstract: Technologies are generally described for an information system configured to manage parking facility resources. The system can create and apply models and profiles regarding customers, parking space usage, access patterns, events, traffic, and other factors related to the parking facility. Parking facility operators may use the models to seek optimized revenues or profits. Increased revenue for parking facility operators may be supported by allocating resources to longer staying and better paying customers. New opportunities such as reselling, auctions, or options may further improve revenue generation for parking facilities. Customers may interface with the information system for availability queries, interactive reservation, and various other functions that may improve convenience, security, privacy, and service quality for the customers as well as for neighboring businesses and venues. Improved efficiency in parking facility resource consumption may reduce street traffic congestion.

Abstract: Technologies are generally described for voice to text to voice processing. An audio signal can be preprocessed and translated into text prior to being processed in the textual domain. The text domain processing or subsequent text to voice regeneration can seek to improve clarity, correct grammar, adjust vocabulary level, remove profanity, correct slang, alter dialect, alter accent, or provide other modifications of various oral communication characteristics. The processed text may be translated back into the audio domain for delivery to a listener. The processing at each stage may be driven by a set of objectives and constraints set by the speaker, the listener, a third party, or any combination of explicit or implicit participants. The voice processing may translate the voice content from a specific human language to the same human language with various improvements. The processing may also involve translation into one or more other languages.

Abstract: Techniques are generally described related to modeling a wireless communication system that includes multiple communication connections. Example systems, apparatuses, methods and processes may include one or more of identifying a first parameter and a first operational characteristic of interest of a first one of the communication connections, activating the first one of the communication connections based on the first parameter, collecting data associated with the first parameter and the first operational characteristic of interest when the first one of the communication connections is active; applying a statistical technique to the collected data to establish a model, and validating the model.

Abstract: Technologies are generally described for a hardware cryptographic unit that employs hardware public physically unclonable functions. A source computer can encrypt a message using a simulation of a hardware cryptographic unit. The encrypted message can then be sent to a destination computer. The destination computer can then use the hardware cryptographic unit to decrypt the message. The source computer can use a simulation of the hardware cryptographic unit to transform an input value into a simulation output. The simulation output can be transmitted from the source computer to the destination computer where all possible input values can be rapidly run through the hardware cryptographic unit until the output of the hardware cryptographic unit matches the simulated output. The input value that generated the matching output is now a shared secret between the source computer and destination computer without ever having been transmitted in the clear over the communication channel.

Abstract: The present disclosure generally relates to methods for improving wireless communications. Example embodiments include placing a wireless communication obstacle at an optimal or approximately optimal position to improve one or more characteristics of a wireless communication link between two wireless communication devices. The wireless communication obstacle may be adapted to absorb or reflect one or more wireless communications from other wireless communication devices to prevent and/or reduce interference with the wireless communication link between the two wireless communication devices.

Abstract: Techniques are generally described for selecting input vectors that reduce or minimize leakage current for a plurality of integrated circuits (ICs) with the same design, but that differ due to manufacturing variability. In various embodiments, the techniques include determining at least one starting input vector that reduces leakage current in a respective one of N instances of the ICs, and selecting from the determined at least one starting input vector of each respective one of the N instances, a set R of representative input vectors. Some of the embodiments then use each of the representative input vectors in the set R to determine at least a particular input vector to apply to input terminals of an IC in the plurality of ICs to reduce or minimize leakage current in the IC. Additional variants and embodiments may also be disclosed.