Patents by Inventor Mirella Marsella
Mirella Marsella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8553460Abstract: Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.Type: GrantFiled: January 10, 2012Date of Patent: October 8, 2013Assignee: Atmel CorporationInventors: Stefano Surico, Mirella Marsella, Monica Marziani, Mauro Chinosi
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Publication number: 20120106250Abstract: Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.Type: ApplicationFiled: January 10, 2012Publication date: May 3, 2012Applicant: ATMEL CORPORATIONInventors: Stefano Surico, Mirella Marsella, Monica Marziani, Mauro Chinosi
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Patent number: 8120963Abstract: Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.Type: GrantFiled: August 4, 2009Date of Patent: February 21, 2012Assignee: Atmel CorporationInventors: Stefano Surico, Mirella Marsella, Monica Marziani, Mauro Chinosi
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Patent number: 7882405Abstract: A flash memory device includes a flash memory array, a set of non-volatile redundancy registers, a serial interface, and testing logic coupled to the serial interface, the testing logic configured to accept a set of serial commands from an external tester; erase the array; program the array with a test pattern; read the array and compare the results with expected results to identify errors; determine whether the errors can be repaired by substituting a redundant row or column of the array, and if so, generate redundancy information; and program the redundancy information into the non-volatile redundancy registers.Type: GrantFiled: February 16, 2007Date of Patent: February 1, 2011Assignee: Atmel CorporationInventors: Riccardo Riva Reggiori, Fabio Tassan Caser, Mirella Marsella, Monica Marziani
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Publication number: 20090290424Abstract: Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.Type: ApplicationFiled: August 4, 2009Publication date: November 26, 2009Inventors: Stefano Surico, Mirella Marsella, Monica Marziani, Mauro Chinosi
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Patent number: 7570519Abstract: Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.Type: GrantFiled: September 19, 2005Date of Patent: August 4, 2009Assignee: Atmel CorporationInventors: Stefano Surico, Mirella Marsella, Monica Marziani, Mauro Chinosi
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Patent number: 7505326Abstract: A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a coupling characteristic of the word lines and selector gates. The transient state is configured to minimize coupling between the word lines and the gates of the selectors so that a state of each selector remains unchanged during the transient state.Type: GrantFiled: October 31, 2006Date of Patent: March 17, 2009Assignee: ATMEL CorporationInventors: Stefano Sivero, Mirella Marsella, Mauro Chinosi, Giorgio Bosisio
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Patent number: 7456678Abstract: An apparatus and method for providing a temperature compensated reference current in an electronic device is disclosed. The temperature compensated reference current is compensated for temperature and other circuit variations. The reference current is provided by an improved reference current generator and may be used in a memory device or any other desired circuit.Type: GrantFiled: October 10, 2006Date of Patent: November 25, 2008Assignee: Atmel CorporationInventors: Marco Passerini, Stefano Sivero, Mirella Marsella, Maria Mostola
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Publication number: 20080201623Abstract: A flash memory device includes a flash memory array, a set of non-volatile redundancy registers, a serial interface, and testing logic coupled to the serial interface, the testing logic configured to accept a set of serial commands from an external tester; erase the array; program the array with a test pattern; read the array and compare the results with expected results to identify errors; determine whether the errors can be repaired by substituting a redundant row or column of the array, and if so, generate redundancy information; and program the redundancy information into the non-volatile redundancy registers.Type: ApplicationFiled: February 16, 2007Publication date: August 21, 2008Applicant: ATMEL CORPORATIONInventors: Riccardo Riva Reggiori, Fabio Tassan Caser, Mirella Marsella, Monica Marziani
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Publication number: 20080101124Abstract: A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a coupling characteristic of the word lines and selector gates. The transient state is configured to minimize coupling between the word lines and the gates of the selectors so that a state of each selector remains unchanged during the transient state.Type: ApplicationFiled: October 31, 2006Publication date: May 1, 2008Applicant: ATMEL CORPORATIONInventors: Stefano Sivero, Mirella Marsella, Mauro Chinosi, Giorgio Bosisio
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Publication number: 20080084240Abstract: An apparatus and method for providing a temperature compensated reference current in an electronic device is disclosed. The temperature compensated reference current is compensated for temperature and other circuit variations. The reference current is provided by an improved reference current generator and may be used in a memory device or any other desired circuit.Type: ApplicationFiled: October 10, 2006Publication date: April 10, 2008Applicant: ATMEL CORPORATIONInventors: Marco Passerini, Stefano Sivero, Mirella Marsella, Maria Mostola
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Patent number: 7269058Abstract: A system and method for preserving an error margin for a non-volatile memory that includes a memory cell, a reference cell coupled to a reference current mirror configured to mirror current through the reference cell. The system comprises a memory current mirror coupled to the memory cell and configured to mirror current through the memory cell. A sense amplifier has a first and a second input. The first input is coupled to the reference current mirror and the second input is coupled to the memory current mirror. The sense amplifier is configured to compare a voltage across the memory cell with a voltage across the reference cell.Type: GrantFiled: May 9, 2005Date of Patent: September 11, 2007Assignee: Atmel CorporationInventors: Massimiliano Frulio, Fabio Tassan Caser, Lorenzo Bedarida, Mirella Marsella
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Patent number: 7249215Abstract: System for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation.Type: GrantFiled: December 7, 2006Date of Patent: July 24, 2007Assignee: Atmel CorporationInventors: Stefano Surico, Simone Bartoli, Mirella Marsella, Giorgio Bosisio
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Patent number: 7242242Abstract: A current mirror comprising: current source; a first p-channel transistor having a source coupled to operating potential, and a gate and drain coupled to current source; a second p-channel transistor having a source coupled to operating potential, a gate coupled to gate of first p-channel transistor, and a drain; a zero-threshold p-channel transistor having a source coupled to drain of second p-channel transistor, a gate coupled to gate of first p-channel transistor, and a drain; a first n-channel transistor having a source coupled to ground, and a gate and drain coupled to drain of zero-threshold p-channel transistor; a second n-channel transistor having a source coupled to ground, a gate coupled to gate of first n-channel transistor, and a drain; and a zero-threshold n-channel transistor having a source coupled to drain of second n-channel transistor, a gate coupled to gate of first n-channel transistor, and a drain coupled to current-output node.Type: GrantFiled: March 29, 2006Date of Patent: July 10, 2007Assignee: Atmel CorporationInventors: Lorenzo Bedarida, Danut Manea, Mirella Marsella, Andrea Sacco
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Patent number: 7236050Abstract: A current mirror comprising: a current source; a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel transistor, and a drain; a first n-channel MOS transistor having a source coupled to ground, and a gate and a drain coupled to the drain of the second p-channel transistor; a zero-threshold n-channel MOS transistor having a drain coupled to a current-output node, a gate coupled to the gate of the first n-channel transistor, and a source; and a second n-channel MOS transistor having a source coupled to ground, and a gate coupled to the gate of the first n-channel transistor and a drain coupled to the source of the zero-threshold n-channel transistor.Type: GrantFiled: March 29, 2006Date of Patent: June 26, 2007Assignee: Atmel CorporationInventors: Lorenzo Bedarida, Danut Manea, Mirella Marsella, Andrea Sacco
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Publication number: 20070083699Abstract: System for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation.Type: ApplicationFiled: December 7, 2006Publication date: April 12, 2007Inventors: Stefano Surico, Simone Bartoli, Mirella Marsella, Giorgio Bosisio
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Patent number: 7181565Abstract: Method and system for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a read-only memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation. In another aspect, one or more selected configuration values not stored in a ROM are changed if a tested flash memory operation is not within desired specifications.Type: GrantFiled: November 10, 2005Date of Patent: February 20, 2007Assignee: Atmel CorporationInventors: Stefano Surico, Simone Bartoli, Mirella Marsella, Giorgio Bosisio
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Publication number: 20060253644Abstract: Method and system for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a read-only memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation. In another aspect, one or more selected configuration values not stored in a ROM are changed if a tested flash memory operation is not within desired specifications.Type: ApplicationFiled: November 10, 2005Publication date: November 9, 2006Inventors: Stefano Surico, Simone Bartoli, Mirella Marsella, Giorgio Bosisio
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Publication number: 20060250851Abstract: Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.Type: ApplicationFiled: September 19, 2005Publication date: November 9, 2006Inventors: Stefano Surico, Mirella Marsella, Monica Marziani, Mauro Chinosi
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Publication number: 20060170489Abstract: A current mirror comprising: a current source; a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel transistor, and a drain; a first n-channel MOS transistor having a source coupled to ground, and a gate and a drain coupled to the drain of the second p-channel transistor; a zero-threshold n-channel MOS transistor having a drain coupled to a current-output node, a gate coupled to the gate of the first n-channel transistor, and a source; and a second n-channel MOS transistor having a source coupled to ground, and a gate coupled to the gate of the first n-channel transistor and a drain coupled to the source of the zero-threshold n-channel transistor.Type: ApplicationFiled: March 29, 2006Publication date: August 3, 2006Inventors: Lorenzo Bedarida, Danut Manea, Mirella Marsella, Andrea Sacco