Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. In the case where the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, in the case where the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold.

Abstract: A system to manage out-of-order traffic in an interconnect network has initiators that provide requests through the interconnect network to memory resource targets and provide responses back through the interconnect network. The system includes components upstream the interconnect network to perform response re-ordering, which include memory to store responses from the interconnect network and a memory map controller to store the responses on a set of logical circular buffers. Each logical circular buffer corresponds to an initiator. The memory map controller computes an offset address for each buffer and stores an offset address of a given request received on a request path. The controller computes an absolute write memory address where responses are written in the memory, the response corresponding to the given request based on the given request offset address.

Abstract: The operation of a FIFO buffer memory includes writing the data at input to the memory in a single write location, and making the single write location available for writing an input datum with a shift of the datum written in the single write location to another location of the memory. At each operation of writing of an input datum in the single write location, there is scheduled shifting of the datum written therein to another location, without waiting for a new write request, thus eliminating the combinational constraint between the two operations.

Abstract: In an embodiment, access transactions of at least one module of a system such as a System-on-Chip (SoC) to one of a plurality of target modules, such as memories, are managed by assigning transactions identifiers subjected to a consistency check. If an input identifier to the check has already been issued for the same given target module, to the related identifier/given target module pair the same input identifier is assigned as a consistent output identifier. If, on the contrary, said input identifier to the check has not been already issued or has already been issued for a target module different from the considered one, to the related identifier/given target module pair a new identifier, different from the input identifier, is assigned as a consistent output identifier.

Abstract: A communication system is arranged to interface a plurality of transmission circuits with an interconnection network. Each transmission circuit generates read requests and/or write requests. The communication system includes a first circuit that operates independently of the communication protocol of the interconnection network. In particular, the first circuit includes, a) for each transmission circuit a communication interface configured for receiving the read requests and/or write requests from the respective transmission circuit, b) a segmentation circuit configured for dividing, i.e., segmenting, the read requests and/or write requests received from the transmission circuits into transfer segments, and c) an interleaving circuit configured for generating, via an operation of interleaving of the transfer segments, a series of segments.

Abstract: In an embodiment, access transactions of at least one module of a system such as a System-on-Chip (SoC) to one of a plurality of target modules, such as memories, are managed by assigning transactions identifiers subjected to a consistency check. If an input identifier to the check has already been issued for the same given target module, to the related identifier/given target module pair the same input identifier is assigned as a consistent output identifier. If, on the contrary, said input identifier to the check has not been already issued or has already been issued for a target module different from the considered one, to the related identifier/given target module pair a new identifier, different from the input identifier, is assigned as a consistent output identifier.

Abstract: A device for calculating the quotient q and remainder r of the division (y·k1+x)/k2, wherein k1 and k2 are integers and constant, and wherein x and y are integers. The device comprises a first digital circuit for receiving as input values of y and identifying corresponding values of the quotient qy and the remainder ry of the function y·k1/k2, a second digital circuit for calculating the remainder r of the division, by a) calculating a combined value (x+ry) of the remainder ry and the value of x, b) verifying if the combined value (x+ry) is less than k2, c) correcting the combined value (x+ry) if the verification indicates that the combined value (x+ry) is not less than k2, and d) assigning the corrected combined value (x+ry) to the remainder r, a third digital circuit for calculating the quotient q of the division, by a) correcting the quotient qy if the verification (2206) indicates that the combined value (x+ry) is not less than k2, and b) assigning the corrected quotient qy to the quotient q.

Abstract: A transmitter for generating, starting from a data-packet traffic at input, flows of information to be conveyed via optical signals with different wavelengths towards a plurality of targets in a communications network, the transmitter including: a destination decoder to identify, for each packet in the input packet traffic, a respective destination target in the plurality of targets; a plurality of emitter modules operating at different wavelengths for converting the electrical signals into optical signals; and a de-multiplexer, which is controlled by the destination decoder and is able to drive the emitter modules by sending selectively to each emitter module the electrical signals corresponding to a given packet of the input packet traffic according to the respective destination target identified by the destination decoder. A serialization module is set upstream of the de-multiplexer for converting the packet traffic into a serial flow of bits.

Abstract: The operation of a FIFO buffer memory includes writing the data at input to the memory in a single write location, and making the single write location available for writing an input datum with a shift of the datum written in the single write location to another location of the memory. At each operation of writing of an input datum in the single write location, there is scheduled shifting of the datum written therein to another location, without waiting for a new write request, thus eliminating the combinational constraint between the two operations.

Abstract: A device for calculating the quotient q and remainder r of the division (y·k1+x)/k2, wherein k1 and k2 are integers and constant, and wherein x and y are integers. The device comprises a first digital circuit for receiving as input values of y and identifying corresponding values of the quotient qy and the remainder ry of the function y·k1/k2, a second digital circuit for calculating the remainder r of the division, by a) calculating a combined value (x+ry) of the remainder ry and the value of x, b) verifying if the combined value (x+ry) is less than k2, c) correcting the combined value (x+ry) if the verification indicates that the combined value (x+ry) is not less than k2, and d) assigning the corrected combined value (x+ry) to the remainder r, a third digital circuit for calculating the quotient q of the division, by a) correcting the quotient qy if the verification (2206) indicates that the combined value (x+ry) is not less than k2, and b) assigning the corrected quotient qy to the quotient q.

Abstract: A transmitter for generating, starting from a data-packet traffic at input, flows of information to be conveyed via optical signals with different wavelengths towards a plurality of targets in a communications network, the transmitter including: a destination decoder to identify, for each packet in the input packet traffic, a respective destination target in the plurality of targets; a plurality of emitter modules operating at different wavelengths for converting the electrical signals into optical signals; and a de-multiplexer, which is controlled by the destination decoder and is able to drive the emitter modules by sending selectively to each emitter module the electrical signals corresponding to a given packet of the input packet traffic according to the respective destination target identified by the destination decoder. A serialization module is set upstream of the de-multiplexer for converting the packet traffic into a serial flow of bits.