Abstract: A method for manufacturing a micromechanical system includes creating a sacrificial layer at a substrate surface. A structural material is deposited at a sacrificial layer surface and at a support structure for later supporting the structural material. At least one hole is created in the structural material extending from an exposed surface of the structural material to the surface of the sacrificial layer. The at least one hole leads to a margin region of the sacrificial layer. The sacrificial layer is removed using a removal process through the at least one hole, to obtain a cavity between the surface of the substrate and the structural material. The method also includes filling the at least one hole and a portion of the cavity beneath the at least one hole close to the cavity. A corresponding micromechanical system and a microelectromechanical transducer are also described.

Abstract: In a method of fabricating a semiconductor structure, a carbon containing mask is fabricated over a dielectric layer. The mask exposes the surface of the dielectric layer at least partly in a region between two adjacent conducting lines. A contact hole is etched into the dielectric layer in the region between the two adjacent conducting lines.

Abstract: A method of fabricating an integrated circuit includes providing a hard mask that includes at least one first layer and one second layer. An etching step is patterned using the hard mask, and a removal step is performed using an etchant in order to at least partially remove the first layer. The first layer and the second layer are configured in such a way that the first layer is etched by the etchant with a higher etch rate than the second layer.

Abstract: The present invention provides a manufacturing method for an integrated circuit comprising a multi-layer stack and a corresponding integrated circuit. In the method a first layer is deposited on a substrate in a plasma deposition process in a plasma chamber using a first reaction gas having at least one first gas component which is introduced at a first flow rate into the chamber. Thereafter a second layer is deposited in situ on the first layer in the plasma deposition process in the plasma chamber using a second reaction gas having at least one second gas component which is introduced at a second flow rate into the chamber. In a switching transition period from the first to the second flow rate a transition layer including a gradual composition transition from the first to the second layer is formed.

Abstract: An integrated circuit is disclosed. The integrated circuit includes a substrate, a metal element, the metal element being arranged on the substrate and including a metal material. A composite element is located over to the metal element, the composite element including the metal material and an additive material.

Abstract: In a method of fabricating a semiconductor structure, a carbon containing mask is fabricated over a dielectric layer. The mask exposes the surface of the dielectric layer at least partly in a region between two adjacent conducting lines. A contact hole is etched into the dielectric layer in the region between the two adjacent conducting lines.

Abstract: An integrated circuit is disclosed. The integrated circuit includes a substrate, a metal element, the metal element being arranged on the substrate and including a metal material. A composite element is located over to the metal element, the composite element including the metal material and an additive material.

Abstract: A carbon hard mask layer is applied to a substrate to be patterned by means of a plasma-enhanced deposition process in such a manner that it has a hardness comparable to that of diamond in at least one layer thickness section. During the production of this diamond-like layer thickness section, the parameters used in the deposition are set in such a manner that growth regions which are produced in a form other than diamond-like are removed again in situ by means of subsequent etching processes and that diamond-like regions which are formed are retained.

Abstract: The present invention relates to a method of forming a carbon layer on a substrate. A substrate with a structured surface is provided, the structured surface comprising a sidewall. A plasma is formed from an atmosphere comprising a gaseous hydrocarbon compound. The substrate is processed with the plasma, thereby depositing a carbon layer on the structured surface of the substrate. According to one aspect of the invention, the gaseous hydrocarbon compound comprises a ratio of less than 2:1 between hydrogen and carbon. According to another aspect of the invention, the atmosphere comprises a gaseous additive compound, the gaseous additive compound having an affinity for binding to hydrogen. Accordingly, the plasma comprises a reduced reactive hydrogen content, thus enabling an improved carbon deposition at the sidewall of the structured surface.

Abstract: A method of forming a wiring level and an electrical isolation associated with the wiring level on a surface of a semiconductor wafer comprises the steps of providing the semiconductor wafer having said surface, forming a plurality of electrically conductive wiring lines upon said surface, each of the wiring lines having a spacing with respect to neighboring one of the wiring lines, depositing a first layer of amorphous carbon upon the wiring lines by means of non-conformal plasma enhanced chemical vapor deposition (PECVD), such that air-filled voids formed below the first layer within the spacings between neighboring wiring lines. Alternatively, OSG (organo-silicon glass) or FSG (fluorine doped silicon glass) may be deposited to yield air-filled voids within the spacings. According to an embodiment, the carbon, OSG or FSG layers are used as an IMD-layer (line-to-line isolation), added by a further layer of a dielectric material, which then serves as an ILD-layer (level-to-level isolation).

Abstract: A plasma-enhanced chemical vapor deposition process for depositing relatively high dielectric constant silicon nitride or oxynitride to form an MIM capacitor is described. The flow rate ratios for the silicon nitride layer are: silane-to-ammonia between 1:20 and 6:5 and silane-to-nitrogen flow between 1:40 and 3:5. A pressure in the process chamber is between 260 Pa and 530 Pa. The flow rate ratios for the silicon oxynitride layer are: silane-to-dinitrogen monoxide between 1:2 and 25:4 and silane-to-nitrogen between 1:100 and 1:10. A larger, non-stoichiometric amount of silicon is incorporated in the layers as the flow rate of the silicon precursor is increased. The layers are deposited in substeps in which the deposition is interrupted between successive substeps. The layer is exposed to an oxygen-containing plasma such that electrically conductive regions of the layer are converted into electrically insulating regions as a result of interaction with the plasma.

Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Abstract: The present invention provides a fabrication method for a semiconductor structure in a substrate, the semiconductor structure having at least two regions that are to be patterned differently. A fabrication of a patterned first region in the substrate, so that the semiconductor structure has a non-patterned second region and the patterned first region, is followed by a deposition of a cover layer that grows over the patterned first region, so that the cover layer above the patterned first region forms a closure, which covers over the patterned first region. This is followed by a fabrication of the patterned second region, the patterned first region remaining protected at least by the closure of the cover layer. The final step effected is a removal of the cover layer above the semiconductor structure, which now has two differently patterned regions.

Abstract: A method of forming a wiring level and an electrical isolation associated with the wiring level on a surface of a semiconductor wafer comprises the steps of providing the semiconductor wafer having said surface, forming a plurality of electrically conductive wiring lines upon said surface, each of the wiring lines having a spacing with respect to neighboring one of the wiring lines, depositing a first layer of amorphous carbon upon the wiring lines by means of non-conformal plasma enhanced chemical vapor deposition (PECVD), such that air-filled voids formed below the first layer within the spacings between neighboring wiring lines. Alternatively, OSG (organo-silicon glass) or FSG (fluorine doped silicon glass) may be deposited to yield air-filled voids within the spacings. According to an embodiment, the carbon, OSG or FSG layers are used as an IMD-layer (line-to-line isolation), added by a further layer of a dielectric material, which then serves as an ILD-layer (level-to-level isolation).

Abstract: To produce a mask, a first mask layer (40) is applied to the substrate (10). During or after the deposition of the first mask layer (40), the latter is exposed to an etching step. The etching step is carried out in such a manner that the material of the first mask layer (40) that has been deposited on side flanks (30) of the raised structure (20) is completely removed from the side flanks (30) or is at least in sections completely removed from the side flanks (30). A second mask layer (50) is applied to the first mask layer and to the uncovered side flank sections (150) of the raised structure (20). Then, the first and second mask layers can be patterned so as to complete the mask (60).

Abstract: A method for transferring structures from a photomask into a photoresist layer is disclosed. In one embodiment, the method involves the patterning of a photoresist layer provided on a layer stack having a topology. In order to suppress standing waves in the photoresist layer and the resist swing effect, which causes variations in the feature sizes, a thin, conformal, organic antireflection layer is applied on the layer stack by means of a known CVD method. The photoresist layer can be patterned dimensionally accurately by means of the method. The method is particularly suitable for the patterning of photoresist layers which are provided for the implantation process of source/drain regions of transistors in semiconductor technology.

Abstract: During the patterning of a semiconductor layer, an N-free SiOx layer is produced under an acid-forming photoresist layer in order to prevent a resist degradation. The Si content of the grown SiOx layer being varied in order to set a desired extinction coefficient k and a desired refractive index n. The SiOx layer formation is effected by a vapor phase deposition, SiH4 and O2 being used as starting gases.

Abstract: Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding uses of the etching mask which allow for extremely thin photoresist layers to be employed.

Abstract: A plasma-enhanced chemical vapor deposition process for depositing relatively high dielectric constant silicon nitride or oxynitride to form an MIM capacitor is described. The flow rate ratios for the silicon nitride layer are: silane-to-ammonia between 1:20 and 6:5 and silane-to-nitrogen flow between 1:40 and 3:5. A pressure in the process chamber is between 260 Pa and 530 Pa. The flow rate ratios for the silicon oxynitride layer are: silane-to-dinitrogen monoxide between 1:2 and 25:4 and silane-to-nitrogen between 1:100 and 1:10. A larger, non-stoichiometric amount of silicon is incorporated in the layers as the flow rate of the silicon precursor is increased. The layers are deposited in substeps in which the deposition is interrupted between successive substeps. The layer is exposed to an oxygen-containing plasma such that electrically conductive regions of the layer are converted into electrically insulating regions as a result of interaction with the plasma.

Abstract: Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.