Patents by Inventor Mirng-ji Lii

Mirng-ji Lii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220238353
    Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.
    Type: Application
    Filed: April 1, 2021
    Publication date: July 28, 2022
    Inventors: Mirng-Ji Lii, Chen-Shien Chen, Lung-Kai Mao, Ming-Da Cheng, Wen-Hsiung Lu
  • Patent number: 11393771
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao Chun Liu, Ching-Wen Hsiao, Kuo-Ching Hsu, Mirng-Ji Lii
  • Patent number: 11342291
    Abstract: A semiconductor package includes a semiconductor substrate, an interconnect structure disposed over the substrate, a first passivation layer disposed over an interconnect structure, a contact pad disposed over the first passivation layer, a dummy pattern disposed around the contact pad and over the first passivation layer, and a second passivation layer overlaying the dummy pattern and the contact pad.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Chun Chuang, Hong-Seng Shue, Chen-Nan Chiu, Li-Huan Chu, Mirng-Ji Lii
  • Publication number: 20220149141
    Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 12, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Mirng-Ji Lii, Shang-Yun Tu, Ching-Hui Chen
  • Publication number: 20220140197
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, active devices and transparent conductive patterns. The active devices are formed on the semiconductor substrate. The transparent conductive patterns are formed over the active devices and electrically connected to the active devices. The transparent conductive patterns are made of a metal oxide material. The metal oxide material has a first crystalline phase with a prefer growth plane rich in oxygen vacancy, and has a second crystalline phase with a prefer growth plane poor in oxygen vacancy.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-En Yen, Ming-Da Cheng, Mirng-Ji Lii, Wen-Hsiung Lu, Cheng-Jen Lin, Chin-Wei Kang, Chang-Jung Hsueh
  • Patent number: 11315896
    Abstract: A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Chen-Hua Yu, Sheng-Yu Wu, Yao-Chun Chuang
  • Publication number: 20220077094
    Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap.
    Type: Application
    Filed: November 12, 2021
    Publication date: March 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Yu WU, Ching-Hui CHEN, Mirng-Ji LII, Kai-Di WU, Chien-Hung KUO, Chao-Yi WANG, Hon-Lin HUANG, Zi-Zhong WANG, Chun-Mao CHIU
  • Patent number: 11264342
    Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Ming-Da Cheng, Mirng-Ji Lii, Meng-Tse Chen, Wei-Hung Lin
  • Patent number: 11244919
    Abstract: A package structure is provided comprising a die, a redistribution layer, at least one integrated passive device (IPD), a plurality of solder balls and a molding compound. The die comprises a substrate and a plurality of conductive pads. The redistribution layer is disposed on the die, wherein the redistribution layer comprises first connection structures and second connection structures. The IPD is disposed on the redistribution layer, wherein the IPD is connected to the first connection structures of the redistribution layer. The plurality of solder balls is disposed on the redistribution layer, wherein the solder balls are disposed and connected to the second connection structures of the redistribution layer. The molding compound is disposed on the redistribution layer, and partially encapsulating the IPD and the plurality of solder balls, wherein top portions of the solder balls and a top surface of the IPD are exposed from the molding compound.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Kuo-Ching Hsu, Mirng-Ji Lii
  • Patent number: 11239305
    Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Mirng-Ji Lii, Shang-Yun Tu, Ching-Hui Chen
  • Patent number: 11222859
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first insulating layer formed over a conductive feature and a capacitor structure embedded in the first insulating layer. The semiconductor device also includes a bonding pad formed over the first insulating layer and corresponding to the capacitor structure. The bonding pad has a top surface and a multi-step edge to form at least three corners. In addition, the semiconductor device structure includes a second insulating layer conformally covering the at least three corners formed by the top surface and the multi-step edge of the bonding pad.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Hao Hsu, Wei-Hsiang Tu, Kuo-Chin Chang, Mirng-Ji Lii
  • Patent number: 11211261
    Abstract: A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally bonding two carrier substrates together and simultaneously processing two carrier substrates. The processing includes forming a sacrificial layer over the carrier substrates. Openings are formed in the sacrificial layers and pillars are formed in the openings. Substrates are attached to the sacrificial layer. Redistribution lines may be formed on an opposing side of the substrates and vias may be formed to provide electrical contacts to the pillars. A debond process may be performed to separate the carrier substrates. Integrated circuit dies may be attached to one side of the redistribution lines and the sacrificial layer is removed.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Liang Meng, Wei-Hung Lin, Yu-min Liang, Ming-Che Ho, Hung-Jui Kuo, Chung-Shi Liu, Mirng-Ji Lii
  • Publication number: 20210384152
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a surface. The semiconductor device includes a conductive pad over a portion of the surface. The conductive pad has a curved top surface, and a width of the conductive pad increases toward the substrate. The semiconductor device includes a device over the conductive pad. The semiconductor device includes a solder layer between the device and the conductive pad. The solder layer covers the curved top surface of the conductive pad, and the conductive pad extends into the solder layer.
    Type: Application
    Filed: August 23, 2021
    Publication date: December 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-En YEN, Chin-Wei KANG, Kai-Jun ZHAN, Wen-Hsiung LU, Cheng-Jen LIN, Ming-Da CHENG, Mirng-Ji LII
  • Patent number: 11177228
    Abstract: A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Yu Wu, Ching-Hui Chen, Mirng-Ji Lii, Kai-Di Wu, Chien-Hung Kuo, Chao-Yi Wang, Hon-Lin Huang, Zi-Zhong Wang, Chun-Mao Chiu
  • Patent number: 11177355
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hung-Yi Kuo, Hao-Yi Tsai, Tsung-Yuan Yu, Min-Chien Hsiao, Chao-Wen Shih
  • Publication number: 20210351144
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first insulating layer formed over a conductive feature and a capacitor structure embedded in the first insulating layer. The semiconductor device also includes a bonding pad formed over the first insulating layer and corresponding to the capacitor structure. The bonding pad has a top surface and a multi-step edge to form at least three corners. In addition, the semiconductor device structure includes a second insulating layer conformally covering the at least three corners formed by the top surface and the multi-step edge of the bonding pad.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Hao HSU, Wei-Hsiang TU, Kuo-Chin CHANG, Mirng-Ji LII
  • Publication number: 20210351139
    Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 11, 2021
    Inventors: Chih-Hsiang Tseng, Yu-Feng Chen, Cheng Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Kuo-Ching Hsu, Hong-Seng Shue, Ming-Hong Cha, Chao-Yi Wang, Mirng-Ji Lii
  • Publication number: 20210351076
    Abstract: An embodiment is a package including a first package component. The first package component including a first die attached to a first side of a first interconnect structure, a molding material surrounding the first die, and a second interconnect structure over the molding material and the first die, a first side of the second interconnect structure coupled to the first die with first electrical connectors. The first package component further includes a plurality of through molding vias (TMVs) extending through the molding material, the plurality of TMVs coupling the first interconnect structure to the second interconnect structure, and a second die attached to a second side of the second interconnect structure with second electrical connectors, the second side of the second interconnect structure being opposite the first side of the second interconnect structure.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 11, 2021
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Mirng-Ji Lii, Chien-Hsun Lee, Jiun Yi Wu
  • Patent number: 11158614
    Abstract: An embodiment device includes a first die, a second die electrically connected to the first die, and a heat dissipation surface on a surface of the second die. The device further includes a package substrate electrically connected to the first die. The package substrate includes a through-hole, and the second die is at least partially disposed in the through hole.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung Wei Cheng, Tsung-Ding Wang, Mirng-Ji Lii, Chien-Hsun Lee
  • Patent number: 11152344
    Abstract: An embodiment package-on-package (PoP) device includes a package structure, a package substrate, and a plurality of connectors bonding the package structure to the package substrate. The package structure includes a logic chip bonded to a memory chip, a molding compound encircling the memory chip, and a plurality of conductive studs extending through the molding compound. The plurality of conductive studs is attached to contact pads on the logic chip.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Mirng-Ji Lii, Chien-Hsun Lee, Jiun Yi Wu