Patents by Inventor Mirng-ji Lii
Mirng-ji Lii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220077094Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap.Type: ApplicationFiled: November 12, 2021Publication date: March 10, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sheng-Yu WU, Ching-Hui CHEN, Mirng-Ji LII, Kai-Di WU, Chien-Hung KUO, Chao-Yi WANG, Hon-Lin HUANG, Zi-Zhong WANG, Chun-Mao CHIU
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Patent number: 11264342Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.Type: GrantFiled: January 3, 2020Date of Patent: March 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chung-Shi Liu, Ming-Da Cheng, Mirng-Ji Lii, Meng-Tse Chen, Wei-Hung Lin
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Patent number: 11244919Abstract: A package structure is provided comprising a die, a redistribution layer, at least one integrated passive device (IPD), a plurality of solder balls and a molding compound. The die comprises a substrate and a plurality of conductive pads. The redistribution layer is disposed on the die, wherein the redistribution layer comprises first connection structures and second connection structures. The IPD is disposed on the redistribution layer, wherein the IPD is connected to the first connection structures of the redistribution layer. The plurality of solder balls is disposed on the redistribution layer, wherein the solder balls are disposed and connected to the second connection structures of the redistribution layer. The molding compound is disposed on the redistribution layer, and partially encapsulating the IPD and the plurality of solder balls, wherein top portions of the solder balls and a top surface of the IPD are exposed from the molding compound.Type: GrantFiled: March 28, 2019Date of Patent: February 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Kuo-Ching Hsu, Mirng-Ji Lii
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Patent number: 11239305Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.Type: GrantFiled: May 4, 2020Date of Patent: February 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Yu Wu, Mirng-Ji Lii, Shang-Yun Tu, Ching-Hui Chen
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Patent number: 11222859Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first insulating layer formed over a conductive feature and a capacitor structure embedded in the first insulating layer. The semiconductor device also includes a bonding pad formed over the first insulating layer and corresponding to the capacitor structure. The bonding pad has a top surface and a multi-step edge to form at least three corners. In addition, the semiconductor device structure includes a second insulating layer conformally covering the at least three corners formed by the top surface and the multi-step edge of the bonding pad.Type: GrantFiled: May 5, 2020Date of Patent: January 11, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Hao Hsu, Wei-Hsiang Tu, Kuo-Chin Chang, Mirng-Ji Lii
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Patent number: 11211261Abstract: A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally bonding two carrier substrates together and simultaneously processing two carrier substrates. The processing includes forming a sacrificial layer over the carrier substrates. Openings are formed in the sacrificial layers and pillars are formed in the openings. Substrates are attached to the sacrificial layer. Redistribution lines may be formed on an opposing side of the substrates and vias may be formed to provide electrical contacts to the pillars. A debond process may be performed to separate the carrier substrates. Integrated circuit dies may be attached to one side of the redistribution lines and the sacrificial layer is removed.Type: GrantFiled: August 7, 2018Date of Patent: December 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Liang Meng, Wei-Hung Lin, Yu-min Liang, Ming-Che Ho, Hung-Jui Kuo, Chung-Shi Liu, Mirng-Ji Lii
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Publication number: 20210384152Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a surface. The semiconductor device includes a conductive pad over a portion of the surface. The conductive pad has a curved top surface, and a width of the conductive pad increases toward the substrate. The semiconductor device includes a device over the conductive pad. The semiconductor device includes a solder layer between the device and the conductive pad. The solder layer covers the curved top surface of the conductive pad, and the conductive pad extends into the solder layer.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-En YEN, Chin-Wei KANG, Kai-Jun ZHAN, Wen-Hsiung LU, Cheng-Jen LIN, Ming-Da CHENG, Mirng-Ji LII
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Patent number: 11177228Abstract: A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.Type: GrantFiled: June 10, 2019Date of Patent: November 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sheng-Yu Wu, Ching-Hui Chen, Mirng-Ji Lii, Kai-Di Wu, Chien-Hung Kuo, Chao-Yi Wang, Hon-Lin Huang, Zi-Zhong Wang, Chun-Mao Chiu
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Patent number: 11177355Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region.Type: GrantFiled: April 9, 2019Date of Patent: November 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hung-Yi Kuo, Hao-Yi Tsai, Tsung-Yuan Yu, Min-Chien Hsiao, Chao-Wen Shih
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Publication number: 20210351139Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.Type: ApplicationFiled: July 26, 2021Publication date: November 11, 2021Inventors: Chih-Hsiang Tseng, Yu-Feng Chen, Cheng Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Kuo-Ching Hsu, Hong-Seng Shue, Ming-Hong Cha, Chao-Yi Wang, Mirng-Ji Lii
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Publication number: 20210351076Abstract: An embodiment is a package including a first package component. The first package component including a first die attached to a first side of a first interconnect structure, a molding material surrounding the first die, and a second interconnect structure over the molding material and the first die, a first side of the second interconnect structure coupled to the first die with first electrical connectors. The first package component further includes a plurality of through molding vias (TMVs) extending through the molding material, the plurality of TMVs coupling the first interconnect structure to the second interconnect structure, and a second die attached to a second side of the second interconnect structure with second electrical connectors, the second side of the second interconnect structure being opposite the first side of the second interconnect structure.Type: ApplicationFiled: July 19, 2021Publication date: November 11, 2021Inventors: Chen-Hua Yu, Kuo-Chung Yee, Mirng-Ji Lii, Chien-Hsun Lee, Jiun Yi Wu
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Publication number: 20210351144Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first insulating layer formed over a conductive feature and a capacitor structure embedded in the first insulating layer. The semiconductor device also includes a bonding pad formed over the first insulating layer and corresponding to the capacitor structure. The bonding pad has a top surface and a multi-step edge to form at least three corners. In addition, the semiconductor device structure includes a second insulating layer conformally covering the at least three corners formed by the top surface and the multi-step edge of the bonding pad.Type: ApplicationFiled: May 5, 2020Publication date: November 11, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Hao HSU, Wei-Hsiang TU, Kuo-Chin CHANG, Mirng-Ji LII
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Patent number: 11158614Abstract: An embodiment device includes a first die, a second die electrically connected to the first die, and a heat dissipation surface on a surface of the second die. The device further includes a package substrate electrically connected to the first die. The package substrate includes a through-hole, and the second die is at least partially disposed in the through hole.Type: GrantFiled: May 15, 2017Date of Patent: October 26, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung Wei Cheng, Tsung-Ding Wang, Mirng-Ji Lii, Chien-Hsun Lee
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Patent number: 11152344Abstract: An embodiment package-on-package (PoP) device includes a package structure, a package substrate, and a plurality of connectors bonding the package structure to the package substrate. The package structure includes a logic chip bonded to a memory chip, a molding compound encircling the memory chip, and a plurality of conductive studs extending through the molding compound. The plurality of conductive studs is attached to contact pads on the logic chip.Type: GrantFiled: July 15, 2019Date of Patent: October 19, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Kuo-Chung Yee, Mirng-Ji Lii, Chien-Hsun Lee, Jiun Yi Wu
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Patent number: 11133274Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.Type: GrantFiled: June 29, 2020Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
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Publication number: 20210288009Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.Type: ApplicationFiled: May 28, 2021Publication date: September 16, 2021Inventors: Ming-Da Cheng, Yung-Ching Chao, Chun Kai Tzeng, Cheng Jen Lin, Chin Wei Kang, Yu-Feng Chen, Mirng-Ji Lii
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Publication number: 20210280477Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first magnetic element and a second magnetic element over the semiconductor substrate. The semiconductor device structure also includes a first conductive line extending exceeding an edge of the first magnetic element. The semiconductor device structure further includes a second conductive line extending exceeding an edge of the second magnetic element. The second conductive line is electrically connected to the first conductive line.Type: ApplicationFiled: May 24, 2021Publication date: September 9, 2021Inventors: Mill-Jer WANG, Tang-Jung CHIU, Chi-Chang LAI, Chia-Heng TSAI, Mirng-Ji LII, Weii LIAO
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Publication number: 20210265165Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Inventors: Chang-Jung Hsueh, Chen-En Yen, Chin Wei Kang, Kai Jun Zhan, Wei-Hung Lin, Cheng Jen Lin, Ming-Da Cheng, Ching-Hui Chen, Mirng-Ji Lii
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Patent number: 11101233Abstract: A method for forming a semiconductor device is provided. The method includes providing a substrate. The method includes forming a mask layer over a surface of the substrate. The mask layer has an opening over a portion of the surface. The method includes depositing a conductive layer over the surface and the mask layer. The method includes removing the mask layer and the conductive layer over the mask layer. The conductive layer remaining after the removal of the mask layer and the conductive layer over the mask layer forms a conductive pad. The method includes bonding a device to the conductive pad through a solder layer. The conductive pad is embedded in the solder layer.Type: GrantFiled: May 7, 2020Date of Patent: August 24, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-En Yen, Chin-Wei Kang, Kai-Jun Zhan, Wen-Hsiung Lu, Cheng-Jen Lin, Ming-Da Cheng, Mirng-Ji Lii
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Publication number: 20210233883Abstract: A method of forming a semiconductor structure is provided. A layout of a substrate is provided. The layout includes a surface having an inner region and an outer region surrounding the inner region. An under bump metallurgy (UBM) pad region within the outer region is defined. The UBM pad region is partitioned into a first zone and a second zone, wherein the first zone faces towards a center of the substrate, and the second zone faces away from the center of the substrate. The substrate is provided according to the layout, wherein the providing of the substrate includes forming a conductive via in the substrate. The conductive via is disposed outside the second zone and at least partially overlaps the first zone from a top view perspective. A UBM pad is formed over the conductive via and within the UBM pad region.Type: ApplicationFiled: April 13, 2021Publication date: July 29, 2021Inventors: KUO-CHIN CHANG, YEN-KUN LAI, KUO-CHING HSU, MIRNG-JI LII