Abstract: A self-aligned process for locating a stem of a T-shaped gate relative to source and drain contacts of a FET or HEMT. The gate stem is located asymmetrically in some embodiments and in such embodiments the stem of the T-shaped gate is located relative to drain and source contacts of the device by forming a plurality of sidewall spacers, with more sidewall spacers being formed on the drain side of the stem than are formed on the source side of the stem. Additionally the gate stem preferably has a high aspect ratio to improve the performance of the resulting FET or HEMT. Drain and source contacts are preferably formed of an n+ semiconductor material.

Abstract: A method of making a stepped field gate for an FET including forming a first set of layers having a passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer, forming additional sets of layers having alternating passivation layer and etch stop layers, successively removing portions of each set of layers using lithography and reactive ion etching to form stepped passivation layers and a gate foot, applying a mask having an opening defining an extent of a stepped field-plate gate, and forming the stepped field plate gate and the gate foot by plating through the opening in the mask.

Abstract: An interconnect for electrically coupling pads formed on adjacent chips or on packaging material adjacent the chips, with an electrically conductive heat sink being disposed between the pads, the interconnect comprising a metallic membrane layer disposed between two adjacent pads and disposed or bridging over the electrically conductive heat sink so as to avoid making electrical contact with the electrically conductive heat sink. An electroplated metallic layer is disposed on the metallic membrane layer. Fabrication of interconnect permits multiple interconnects to be formed in parallel using fabrication techniques compatible with wafer level fabrication of the interconnects. The interconnects preferably follow a smooth curve to electrically connect adjacent pads and following that smooth curve they bridge over the intervening electrically conductive heat sink material in a predictable fashion.

Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.

Abstract: Systems, methods, and apparatus are disclosed for wideband power amplification in a platform, such as an airplane. An amplifier module may include a first amplification stage. The first amplification stage may comprise a first plurality of amplification circuits. The amplifier module may also include a first plurality of couplers configured to couple an input port to each amplification circuit of the first amplification stage. The amplifier module may include a second amplification stage comprising a second plurality of amplification circuits. The amplifier module may also include a second plurality of couplers configured to couple the first amplification stage to the second amplification stage. The amplifier module may include a third plurality of couplers configured to combine an output of each amplification circuit of the second plurality of amplification circuits into an output signal. The third plurality of couplers may comprise one or more Lange couplers.

Abstract: A method for forming a wafer level heat spreader includes providing a mesh wafer, the mesh wafer having a plurality of openings and mesh regions between the openings, bonding the mesh wafer to a backside of an integrated circuit (IC) wafer, the IC wafer comprising a plurality of circuits; and electroplating a heat sink material through the plurality of openings and onto to the backside of the IC wafer.

Abstract: A cancellation circuit for a simultaneous transmit and receive system includes a variable attenuator, a variable coarse true time delay a variable fine true time delay, the variable fine true time delay having a cancellation signal output, a circulator coupled to a transmit signal and having a receive signal input and having an output having a sum of the receive signal and a leakage signal, the leakage signal being a portion of the transmit signal leaking through the circulator, a 180° hybrid having a delta output having a difference between the sum of the receive signal and a leakage signal and the cancellation signal, and a control circuit coupled to the delta output and the variable attenuator, the variable coarse true time delay, and the variable fine true time delay to adjust an amplitude and phase of the cancellation signal.

Abstract: An operational amplifier includes three transconductance stages (TSs) each having a differential input and a differential output, a first and second resistor coupled between the differential output of the first TS and the differential input of the first TS, a third and fourth resistor coupled between the differential output of the third TS and the differential input of the first TS, a first and second capacitor coupled between the differential output of the third TS and the differential input of the third TS, wherein the first, second, and third TSs each include a differential input amplifier coupled to the differential input of the respective TS, a differential output amplifier coupled to the differential output of the respective TS, and a plurality of Schottky diodes coupled between the differential input amplifier and the differential output amplifier for voltage level shifting.

Abstract: The interface resistance between the source/drain and gate of an HFET may be significantly reduced by engineering the bandgap of the 2DEG outside a gate region such that the charge density is substantially increased. The resistance may be further reduced by using an n+GaN Cap layer over the channel layer and barrier layer such that a horizontal surface of the barrier layer beyond the gate region is covered by the n+GaN Cap layer. This technique is applicable to depletion and enhancement mode HFETs.

Abstract: A method and apparatus for mounting microelectronic chips to a thermal heat sink. The chips are arranged in a desired configuration with their active faces all facing a common direction and with their active faces defining a common planar surface for all of said chips. A metallic material is applied to the chip, preferably by electroplating to backsides of the chips, the metallic material being electro-formed thereon and making void-free contact with the backsides of the chips.

Abstract: A method of making a stepped field gate for an FET including forming a first set of layers having a passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer, forming additional sets of layers having alternating passivation layer and etch stop layers, successively removing portions of each set of layers using lithography and reactive ion etching to form stepped passivation layers and a gate foot, applying a mask having an opening defining an extent of a stepped field-plate gate, and forming the stepped field plate gate and the gate foot by plating through the opening in the mask.

Abstract: A method of fabricating a normally “off” GaN heterostructure field effect transistor having a source and a drain including depositing a passivation layer patterned to cover a channel region between a source and a drain, forming a first opening in the passivation layer, the first opening for defining a gate area in the channel region and the first opening having a first length dimension along a direction of current flow between the source and the drain, and implanting ions in an implant area within the gate area, wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension.

Abstract: A method of fabricating amplifiers, includes monolithically integrating a field-plate transistor and T-gate transistor on a single wafer. A device includes a monolithically integrated field-plate transistor and T-gate transistor on a single wafer.

Abstract: A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist.

Abstract: A semiconductor device comprises one or more transistors and two or more layers of dielectric material encapsulating a front side of said one or more transistors. The gate of each of said one or more transistors is located within a cavity, or air-box, in at least one of the dielectric layers, so that the gate terminal is physically separated from said dielectric material. Such an arrangement may reduce parasitic capacitance. In another arrangement, a semiconductor device comprises one or more gallium nitride high electron mobility transistors and one or more dielectric layers encapsulating a front side of said one or more transistors, wherein the gate terminal of each of said one or more transistors is located within a cavity in at least one of the one or more dielectric layers, separated from said dielectric material.

Abstract: A method of mounting a plurality of semiconductor or microelectronic chips or dies, the method including providing a carrier, temporarily adhering the plurality of semiconductor or microelectronic chips or dies to the carrier with active faces of the chips or dies facing towards the carrier, covering backsides of the chips and filling empty spaces between the chips or dies with a metallic material to thereby define an assembly of the chips or dies and the metallic material, and releasing the assembly from the carrier, wherein each chip or die comprises at least one bonding ring higher than a height of the active face of the respective chip or die or any connections on the active face of the respective chip or die.

Abstract: A method of forming a slanted field plate including forming epitaxy for a FET on a substrate, forming a wall near a drain of the FET, the wall comprising a first negative tone electron-beam resist (NTEBR), depositing a dielectric over the epitaxy and the wall, the wall causing the dielectric to have a step near the drain of the FET, depositing a second NTEBR over the dielectric, wherein surface tension causes the deposited second NTEBR to have a slanted top surface between the step and a source of the FET, etching anisotropically vertically the second NTEBR and the dielectric to remove the second NTEBR and to transfer a shape of the slanted top surface to the dielectric, and forming a gatehead comprising metal on the dielectric between the step and the source of the FET, wherein the gatehead forms a slanted field plate.

Abstract: A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.

Abstract: A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.

Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.