Abstract: A method for sensing real load unbalance in an electrical power system having at least two clock based power sources which are connected for parallel operation combines a real load difference current signal, proportional to the difference in real load currents in corresponding phases of the power sources, with a phase angle signal which is proportional to the phase difference between an external clock signal and an internal clock signal of one of the power sources, to produce an error signal. When this error signal exceeds a predetermined threshold level, a trip signal is produced to indicate that an excessive real load unbalance situation exists.

Abstract: A parallel power system includes at least two DC link variable speed constant frequency power sources each having a plurality of output phases connected to a common bus. The total real error current flowing in the output phases of each of the power sources is monitored and the relative phase angle of the Thevenin voltage of the power sources is controlled in response to the monitored total real error current to reduce the magnitude of this real error current. The reactive error current flowing in at least one of the output phases of each of the power sources is monitored and the relative magnitude of the Thevenin voltage of the power sources is controlled in response to the monitored reactive error current to reduce the magnitude of the reactive error current. For operation at no load, the phase angle control loop is sensitive to both real and reactive error currents.

Abstract: A solid state switching circuit is provided with a first power sharing circuit which incorporates resistive power dissipation elements so that the required dissipated power is shared between a main power transistor and the power sharing circuit. A second power sharing circuit is connected in parallel with a portion of the first power sharing circuit and operates to provide additional resistive power dissipation under certain switch voltage conditions. The use of this second power sharing circuit permits an increase in the required trip time of the main switching transistor or improves the reliability of the power transistors in the main circuit and the first power sharing circuit by lowering transistor stress during transient conditions.

Abstract: A clock control system for a multiple channel electric power system includes a master clock circuit and control circuitry in each parallel connected channel. The channel control circuits are intially phase-locked to a master clock signal. If the master clock signal is out of a preselected frequency range, the individual channel control circuits are decoupled from the master clock signal and one of those circuits produces a backup clock signal. The control circuits in the remaining channels are then phase-locked with the backup clock signal to provide continued parallel system operation.