Abstract: Methods and systems support bridging between end devices conforming to a legacy bus specification and a host processor using an updated bus specification, for example the latest PCIe specification or Compute Express Link (CXL). A hardware bridge can serve as an intermediary between the legacy I/O devices and the host processor. The hardware bridge has a hardware infrastructure and performs a hardware virtualization of the legacy I/O devices such that their legacy hardware is emulated by a virtual interface. The hardware bridge can surface the virtual interface to the host processor, enabling these I/O devices to appear to the host processor as an end device communicating in accordance with the updated bus specification. The hardware virtualization can involve emulating the I/O devices using scalable I/O Virtualization (SIOV) queue pairs, providing flexible and efficient translation between the legacy and updated specifications.

Abstract: A memory controller of a sender node issues an instruction of a trans-fabric instruction set of instructions to a receiver node across a communication fabric that supports memory semantic operations, to cause a given transaction to be performed at the receiver node in response to the issued instruction.

Abstract: In an example implementation according to aspects of the present disclosure, a memory controller is disclosed. The memory controller is communicatively coupleable to a memory resource having a plurality of memory resource regions, which may be associated with a plurality of computing resources. The memory controller may include a memory resource interface to communicatively couple the memory controller to the memory resource and a computing resource interface to communicatively couple the memory controller to the plurality of computing resources. The memory controller may further include a memory resource memory management unit to manage the memory resource.

Abstract: In an example implementation according to aspects of the present disclosure, a memory controller is disclosed. The memory controller is communicatively coupleable to a memory resource having a plurality of memory resource regions, which may be associated with a plurality of computing resources. The memory controller may include a memory resource interface to communicatively couple the memory controller to the memory resource and a computing resource interface to communicatively couple the memory controller to the plurality of computing resources. The memory controller may further include a memory resource memory management unit to manage the memory resource.

Abstract: A memory controller of a sender node issues an instruction of a trans-fabric instruction set of instructions to a receiver node across a communication fabric that supports memory semantic operations, to cause a given transaction to be performed at the receiver node in response to the issued instruction.

Abstract: An example system includes a memory controller; a memory bus coupled to the memory controller; and a dual inline memory module (DIMM) coupled to the memory controller through the memory bus. The DIMM includes a dynamic random access memory (DRAM) portion; a storage portion; and a gate array portion coupled to the memory bus to detect memory access signals and to store information related to the memory access signals on the storage portion.

Abstract: A memory controller of a sender node issues an instruction of a trans-fabric instruction set of instructions to a receiver node across a communication fabric that supports memory semantic operations, to cause a given transaction to be performed at the receiver node in response to the issued instruction.

Abstract: In an example implementation according to aspects of the present disclosure, a computing system includes a memory resource having a plurality of memory resource regions and a plurality of computing resources. The plurality of computing resources are communicatively coupleable to the memory resource. Each computing node may include a native memory management unit to manage a native memory on the computing resource and a memory resource memory management unit to manage the memory resource region of the memory resource associated with the computing resource.

Abstract: In an example implementation according to aspects of the present disclosure, a memory controller is disclosed. The memory controller is communicatively coupleable to a memory resource having a plurality of memory resource regions, which may be associated with a plurality of computing resources. The memory controller may include a memory resource interface to communicatively couple the memory controller to the memory resource and a computing resource interface to communicatively couple the memory controller to the plurality of computing resources. The memory controller may further include a memory resource memory management unit to manage the memory resource.

Abstract: A memory controller of a sender node issues an instruction of a trans-fabric instruction set of instructions to a receiver node across a communication fabric that supports memory semantic operations, to cause a given transaction to be performed at the receiver node in response to the issued instruction.

Abstract: A receiver node receives, over a communication fabric, a transaction packet that includes an identifier of a sender node and an identifier of a process at the sender node, the transaction packet sent by the process for a transaction. The receiver node performs authentication for the transaction based on the identifier of the process and the identifier of the sender node.

Abstract: An example system includes a memory controller; a memory bus coupled to the memory controller; and a dual inline memory module (DIMM) coupled to the memory controller through the memory bus. The DIMM includes a dynamic random access memory (DRAM) portion; a storage portion; and a gate array portion coupled to the memory bus to detect memory access signals and to store information related to the memory access signals on the storage portion.

Abstract: Programmable address mapping and memory access operations are disclosed. An example apparatus includes an address translator to translate a first host physical address to a first intermediate address. The example apparatus also includes a programmable address decoder to decode the first intermediate address to a first hardware memory address of a first addressable memory location in a memory, the programmable address decoder to receive a first command to associate the first host physical address with a second addressable memory location in the memory by changing a mapping between the first intermediate address and a second hardware memory address of the second addressable memory location.

Abstract: According to an example, data for a memcached server is replicated to a memcached replication server. Data operations for the memcached server may be filtered for backing up data to the memcached replication server.

Abstract: Disclosed herein are an apparatus, an integrated circuit, and method to cache objects. At least one hash table of a circuit comprises a predetermined arrangement that maximizes cache memory space and minimizes a number of cache memory transactions. The circuit handles requests by a remote device to obtain or cache an object.

Abstract: According to an example, data for a memcached server is replicated to a memcached replication server. Data operations for the memcached server may be filtered for backing up data to the memcached replication server.

Abstract: An apparatus and method that permits signal traces of different widths and the same impedance to be placed on the same layer of a printed circuit board (PCB). Alternatively, signal traces of different impedances but the same width may be placed on the same layer of the PCB. Ground and power planes are paired on adjacent layers of the PCB with a portion of the power plane relative to the ground plane removed. Signal traces of the same width and different impedances or vice-versa can be placed on the same layer because each signal trace is referenced to different planes.

Abstract: A multi-layer circuit board includes a first layer having at least first and second conductive traces of different widths and the same impedance. One of a first power plane and first ground plane has a void region such that the first conductive trace is spaced apart from the first power plane by a first thickness, and the second conductive trace is spaced apart from the first ground plane by a second, different thickness.

Abstract: A socket is for use in an electronic system to hold a circuit board module that has spaced electrical pads proximate to two opposite edges thereof. The socket includes a base and electrical conductors. The base has rectangularly arranged peripheral portions and is for receiving the circuit board module. The electrical conductors align with the electrical pads on the circuit board module. At least portions of the electrical conductors are disposed on respectively opposite ones of the peripheral portions to contact at least portions of corresponding ones of the aligned electrical pads on the circuit board module when the circuit board module is held in the socket.

Abstract: A first signal passes through a first layer of a circuit apparatus at a first propagation speed, and a second signal passes through a second layer of the circuit apparatus at a second propagation speed different from the first propagation speed.