Abstract: A modular, expandable, multi-port main memory system that includes multiple point-to-point switch interconnections and a highly-parallel data path structure that allows multiple memory operations to occur simultaneously. The main memory system includes an expandable number of modular Memory Storage Units, each of which are mapped to a portion of the total address space of the main memory system, and may be accessed simultaneously. Each of the Memory Storage Units includes a predetermined number of memory ports, and an expandable number of memory banks, wherein each of the memory banks may be accessed simultaneously. Each of the memory banks is also modular, and includes an expandable number of memory devices each having a selectable memory capacity. All of the memory devices in the system may be performing different memory read or write operations substantially simultaneously and in parallel.

Abstract: A data by-pass system for a hierarchical, multi-level, memory is disclosed. The by-pass system provides by-pass interfaces between storage devices located at predetermined levels within the memory hierarchy. The hierarchical memory system of the preferred embodiment includes a main memory coupled to multiple first storage devices that each stores addressable portions of data signals retrieved from the main memory. To facilitate a more efficient transfer of data between the various storage devices in the memory system, at least one by-pass interface coupling associated ones of the first storage devices is provided. Data retrieved from a target one of the first storage devices in response to a main memory request can be routed to a different requesting one of the first storage devices via the by-pass system without requiring the use of the main memory data interfaces.

Abstract: A hierarchical memory structure includes a directory-based main memory coupled to multiple first storage devices, each to store data signals retrieved from the main memory. Ones of the first storage devices are further respectively coupled to second storage devices, each to store data signals retrieved from the respectively coupled first storage devices. Fetch requests to retrieve data signals are issued by ones of the storage devices to the main memory. In response, the main memory determines where the most recent data copy resides, and issues a return request, if necessary to retrieve that copy for the requesting storage device. A speculative return generation logic circuit is coupled to at least two of the first storage devices to intercept the fetch requests. In response to an intercepted request, the speculative return generation logic circuit generates a speculative return request directly to one or more of the other coupled first storage devices.

Abstract: A method and apparatus for generating test input for a logic simulator by providing a template that allows a test designer to more efficiently enter the desired test conditions. The template is preferably arranged to facilitate the definition of test cases, and in particular, parallel type test cases. One region of the template is preferably dedicated to one section of a circuit design, and another region is dedicated to another section of the circuit design. When the regions are positioned side-by-side, for example, the test designer can easily identify the test conditions that are applied to the various circuit sections, including the relationships therebetween. Once the test conditions are entered, the template is processed and the desired test input is automatically generated.

Abstract: A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/0) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line.

Abstract: A memory request management system for use with a memory system employing a directory-based cache coherency scheme is disclosed. The memory system includes a main memory coupled to receive requests from multiple cache memories. Directory-based logic is used to determine that some requests presented to the main memory can not be completed immediately because the most recent copy of the requested data must be retrieved from another cache memory. These requests are stored in a temporary storage structure and identified as “deferred” requests. Subsequently, predetermined ones of the memory requests that are requesting access to the same main memory address as is being requested by any deferred request are also deferred. When a data retrieval operation is completed, an associated request is designated as undeferred so that processing for that request may be completed, and the request may be removed from the temporary storage structure.

Abstract: A high-speed memory system is disclosed for use in supporting a directory-based cache coherency protocol. The memory system includes at least one data system for storing data, and a corresponding directory system for storing the corresponding cache coherency information. Each data storage operation involves a block transfer operation performed to multiple sequential addresses within the data system. Each data storage operation occurs in conjunction with an associated read-modify-write operation performed on cache coherency information stored within the corresponding directory system. Multiple ones of the data storage operations may be occurring within one or more of the data systems in parallel. Likewise, multiple ones of the read-modify-write operations may be performed to one or more of the directory systems in parallel. The transfer of address, control, and data signals for these concurrently performed operations occurs in an interleaved manner.

Abstract: A system and method for testing and initializing a memory including multiple memory banks or a memory module partitioned into logical memory units. A plurality of memory exerciser testers are provided, one for each of the plurality of memory banks. Each of the memory exerciser testers includes an address generator to generate a sequence of memory bank addresses to successively address each of the memory banks in a cyclic manner, while each of the address generators concurrently addresses a different one of the memory banks. A data pattern generator is coupled to a corresponding one of the address generators to receive a data pattern control signal upon each output of each of the memory bank addresses generated by its corresponding address generator. The data pattern generator outputs a unique data pattern to the memory bank identified by the memory bank address in response to each occurrence of the data pattern control signal.

Abstract: A programmable address translation system for a modular main memory is provided. The system is implemented using one or more General Register Arrays (GRAs), wherein each GRA performs logical-to-physical address translation for a predetermined address range within the system. Predetermined bits of a logical address are used to address a GRA associated with the logical address range. Data bits read from the GRA are then substituted for the predetermined bits of the logical address to form the physical address. In this manner, non-contiguous addressable banks of physical memory may be mapped to a selectable contiguous address range. By including within the GRA Address a number N of logical address bits used to address contiguous logical addresses, an address translation mechanism is provided which may be programmed to perform between 2-way and 2N-way address interleaving.

Abstract: Method and apparatus for synchronizing the execution of the two or more test lists at desired synchronization points, while allowing the test lists to execute in a non-deterministic manner between the synchronization points is disclosed. A test driver is provided for executing each test list, and a run controller is provided for monitoring the execution of each test list. To synchronize the execution of the two or more test lists, the run controller halts the execution of each test list as each test driver assumes a predetermined state. Once all of the test lists are halted, the test lists are synchronized. Once synchronized, selected test drivers are restarted to continue execution of the corresponding test lists in a relatively non-deterministic manner.

Abstract: A method and apparatus for providing for serially transmitting partitioning information between system partitions, and between system partitions and the corresponding data processing resources. Serial transmission may allow the partitioning information to be transmitted using a single I/O ASIC pin, and a single PC board trace. In addition to reducing the required number of I/O ASIC pins and PC board traces, the present invention may increase the overall reliability of the partitioning mechanism.

Abstract: A test driver for use in validating an electronic circuit design is disclosed. The test driver not only provides stimulus and verifies the response of a circuit design, but also responds appropriately to requests provided by the circuit design. The test driver may also modify a selected portion of a data element before returning the data element to the circuit design. Under some test conditions, this helps verify that the test driver did in fact gain access to a data element during a particular test case.

Abstract: Data transfer scheme wherein data transfer rates can be effectively doubled with no increase in the clock speed of the interface. This is accomplished by allowing more than one data transfer to occur on a single clock cycle. This transfer scheme increases the transfer rate of the interface by multiplexing two data groups on the same interface. These data groups are transmitted from a source phase latch at approximately the same time as two strobe signals which have low skew with respect to the data. The master and slave strobe signals are logically combined to create an even latch enable signal and an odd latch enable signal that are used to latch and de-multiplex the multiplexed data groups at a receiving end of a pair of flow-though source synchronous latches.

Abstract: A system and method for reducing data transfer delays in a transaction processing system is provided. The system includes a plurality of devices each having an associated local memory, and a supervisory memory module having a main storage module for storing data segments and a directory storage for maintaining ownership status of each data segment stored in the main storage module and the local memories. A second device makes a request for a data segment which is stored in a first local memory of a first device. A data transfer request for the requested data segment is transferred from the second device to the supervisory memory module, where the data transfer request includes an identifier requesting permission to modify the requested data segment. The requested data and a data transfer response is delivered to the second device upon receipt of the data transfer request, where the data transfer response provides modification privileges of the requested data segment to the second device.

Abstract: A system and method for providing direct transfers of data segments between devices having local memories without the need for first transferring the data to a central supervisory memory to maintain cache coherency. Direct data transfers are performed from a first local memory of a first device to a second local memory in a second device in a transaction processing system that includes a main memory to provide supervisory storage capability for the transaction processing system, and a directory storage for maintaining ownership status of each data segment of the main memory. A data transfer of a requested data segment is requested by the second device to obtain the requested data segment stored in the first local memory of the first device. The requested data segment is removed from the first local memory in response to the data transfer request, and is directly transferred to the second local memory of the second device.

Abstract: Flush apparatus for a dual multi-processing system. Each dual multi-processing system has a number of processors, with each processor having a store in first-level write through cache to a second-level cache. A third-level memory is shared by the dual system with the first-level and second-level caches being globally addressable to all of the third-level memory. Processors can write through to the local second-level cache and have access to the remote second-level cache via the local storage controller. A coherency scheme for the dual system provides each second-level cache with indicators for each cache line showing which ones are valid and which ones have been modified or are different than what is reflected in the corresponding third level memory.

Abstract: A method of interfacing multiple requests using a request hold register, a multiplexer and a snapshot register with multiple requests directed into both the request hold register and a multiplexer which prevents forwarding the requests to the snapshot register if the snapshot register is not in a receiving condition but if the snapshot register is in a receiving condition allows the request to immediately enter snapshot register without having to wait for the next clock cycle.

Abstract: A system and method for enabling a multiprocessor system employing a memory hierarchy to identify data units or locations being used as software locks. The memory hierarchy comprises a main memory having a plurality of data units, a plurality of caches that operate independently of each other, and at least one coherent domain interfaced to each cache. Each coherent domain comprises at least two processors. The main memory maintains coherency of data among the plurality of caches using a directory that maintains information about each data line. The system of the present invention allows a requesting agent, such as a processor or cache, to request a data unit without specifying the type of ownership, where ownership may be exclusive or shared. The directory includes history information that defines the previous access pattern of the requested data unit.

Abstract: A system and method for optimizing the amount of time it takes for a requestor (device) to receive data from a memory storage unit in a multi-requestor bus environment. The present invention provides a unidirectional response signal, referred to as an early warning signal, sent from a memory storage unit to a device, sometime after that device has executed a fetch request for data, to alert the device that the data is forthcoming. This early warning signal allows the device to arbitrate for the data bus so that when the data arrives, the device will have exclusive ownership of the data bus to accept the data immediately. The present invention comprises a main memory, a cache memory, one or more processor modules, one or more I/O modules, and an early warning bus. The cache memory is connected to the main memory via an interface bus. The processor modules are connected to the cache memory via a processor interface bus. The I/O modules are connected to the main memory via an I/O interface bus.

Abstract: System and method for controlling the flow of messages in a computer system to minimize congestion and prevent deadlocks in communications. The computer system includes a main memory, a plurality of crossbar switches, a plurality of third level caches, and a plurality of input/output modules, which are interconnected via the communications network of the computer system. System and method prevents deadlocks between input/output modules and main memory, and between processors and main memory caused by data needed for making forward progress in processing being trapped behind messages. System and method utilize control signals and auxiliary buffers to hold and redirect messages out of the path of data so that data may flow to the input/output modules and processors when needed, and messages may flow when convenient.